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Scroll Title

anchor	Figure_OV_BD
title	TE0802 Block Diagram

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Scroll Only

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Bootmode signals must be set through DIP Switch S9S1.

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title	Boot Process

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MODE Signal State	MODE1 S1-2(B)	MODE0 S1-1(A)	Boot Mode
MODE[2:0]=000	OFF	OFF	JTAG
MODE[2:0]=001	OFF	ON	not supported
MODE[2:0]=010	ON	OFF	QSPI(32 bit)
MODE[2:0]=011	ON	ON	SD0(2.0)

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anchor	Table_SIP_TestPoint
title	Test Points Information

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Test Point	Signals	Notes
1TP1	+1.1V_LPDDR4
2TP2	+1.8V_MGTRAVTT
3TP3	+1.8V_PL
4TP4	FT_B_TX
5TP5	DP_TX_PWR
6TP6	GND
7TP7	GND
8TP8	PMIC2_SDA
9TP9	PMIC2_TP
10TP10	ONKEY2
11TP11	PMIC2_SCL
12TP12	DP_TX_HPD
13TP13	DP_TX_PWR
14TP14	INT_SCL1
15TP15	INT_SDA1
16TP16	FT_B_RX
17TP17	CLOCKDIST_OE
18TP18	+0.85V_VCCINT
19TP19	+3.3V
20TP20	+1.8V_PS
21TP21	ERR_STATUS
22TP22	+1.2V_PSPLL
23TP23	GND
24TP24	GND
25TP25	PMIC1_SCA
26TP26	PMIC1_SDA
27TP27	ONKEY1
28TP28	PMIC1_TP
29TP29	POR_B
30TP30	PSBATT
31TP31	SRST_B
32TP32	DONE
33TP33	INIT_B
34TP34	VBUS
35TP35	USB_VBUS
36TP36	PROG_B
37TP37	ERR_OUT

On-board Peripherals

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Scroll Title

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title	On-board Peripherals

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Chip/Interface	Designator	Notes
Quad SPI Flash Memory 81199613	U16
LPDDR4 SDRAM 81199613	U13
EEPROM 81199613	U2, U18
USB ULPI PHY 81199613	U22
Ethernet PHY 81199613	U6
FTDI FT2232H 81199613	U17
Clock Generator 81199613	U8
Oscillators	U7, U15, U19, U23, U43
7-Segment Display 81199613	D9
User LED 81199613	LED0...7
Push Button 81199613	BTN1...5
DIP Switch 81199613	S1, S7../S.8

Quad SPI Flash Memory

Page properties

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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Scroll Title

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title	DIP Switches

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Designator	Schematic	Connected to	Functionality	Note
S1AS1-1(A)	MODE0	Pin J16, FPGA Bank 503	DIP	Pulled-down to GND.
S1BS1-2(B)	MODE1	Pin H15, FPGA Bank 503	DIP	Pulled-down to GND.
S1CS1-3(C)	USER_CFG0	Pin A4, FPGA Bank 66	DIP	Pulled-down to GND.
S1DS1-4(D)	USER_CFG1	Pin B4, FPGA Bank 66	DIP	Pulled-down to GND.
S7AS7-1(A)	USER_SW7	Pin M5, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S7BS7-2(B)	USER_SW6	Pin M4, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S7CS7-3(C)	USER_SW5	Pin J2, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S7DS7-4(D)	USER_SW4	Pin K1, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8AS8-1(A)	USER_SW3	Pin L1, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8BS8-2(B)	USER_SW2	Pin M1, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8CS8-3(C)	USER_SW1	Pin P2, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8DS8-4(D)	USER_SW0	Pin P3, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.

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Scroll Title

anchor	Table_TS_AMR
title	Absolute Maximum Ratings

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Symbols	Description	Min	Max	Unit
VIN	Input Supply Voltage (J13)	-3.5	7	V
T_STG	Storage Temperature	-40

50

85

V

°C

Recommended Operating Conditions

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Scroll Title

anchor	Table_TS_ROC
title	Recommended Operating Conditions

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Parameter	Min	Max	Units	Reference Document
VIN	4	5.5	V	Schematic "POWER" (Component: LTC4365ITS8)
T_STG	0	85	°C	Zynq Ultrascale+ Data sheet

Physical Dimensions

Module size: 100 mm × 100 mm. Please download the assembly diagram for exact numbers.

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Scroll Title

anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

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Trenz Shop TE0702 TE0802 Overview Page
English page	German page

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title	Document Change History

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Date

Revision

Contributor

Description

Page info

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Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

Technical Specifications updated

Typo correction

2020-11-19

v.65

Pedram Babakhani

initial release

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all

Page info

infoType	Modified users
type	Flat
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Trenz Electronic Documentation

Versions Compared

Old Version 62

New Version Current

Key

On-board Peripherals

Quad SPI Flash Memory

Recommended Operating Conditions

Physical Dimensions