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Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface(each DDR 16bit separate)
512 Mbit (64 MByte) QSPI Flash
3 x Samtec Razor Beam LSHM B2B, 260 terminals total
- 60 x HR I/Os
- 84 x HP I/Os
- 8 x GTH transceiver lanes (TX/RX)
- 2 x MGT external clock inputs
Clocking
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator
All power supplies on-board, single power source operation
Evenly spread supply pins for optimized signal integrity
Size: 40 x 50 mm
3 mm mounting holes for skyline heat spreader
Rugged for industrial applications

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anchor	Figure_2
title	Figure 2: TE0841-02 main components

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draw.io Diagram

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Photo shows similar TE0841-01

Xilinx Kintex UltraScale FPGA, U1
Ultra performance oscillator @25.000000 MHz, U3
12A PowerSoC DC-DC converter (0.95V), U14
12A PowerSoC DC-DC converter (0.95V), U7
Low-jitter precision LVDS oscillator @200.0000 MHz, U11
Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
Samtec Razor Beam™ LSHM-150 B2B connector, JM1
Samtec Razor Beam™ LSHM-150 B2B connector, JM2
Samtec Razor Beam™ LSHM-130 B2B connector, JM3
Programmable quad clock generator, U2
64 MByte QSPI Flash, U6
8 Gbit DDR4 SDRAM, U4
8 Gbit DDR4 SDRAM, U5
System Controller CPLD, U18Programmable Clock Generator
Low-dropout (LDO) linear regulator (MGTAUX), U9
Ultra-low power low-dropout (LDO) regulator (VBATT), U19

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Storage device name	Content	Notes
System Controller CPLD	Default firmware	-
OTP Flash area	Empty	Not programmed
Quad clock generator OTP area	Empty	programmed	on PCB REV02 and newerNot programmed

Table 1: TE0841-02 module initial delivery state of programmable on-board devices

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The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock Source	Frequency	Signal Name	Clock Destination	Notes
U3, SiT8208AI	25.000000 MHz	CLK	Si5338A PLL U2, pin 3 (IN3)	-
U11, DSC1123DL5	200.0000 MHz	CLK200M_P	FPGA bank 45, pin R25	Enable by FPGA bank 65, pin AF24 Signal: 'ENOSC'
U11, DSC1123DL5	200.0000 MHz	CLK200M_N	FPGA bank 45, pin R26	Enable by FPGA bank 65, pin AF24 Signal: 'ENOSC'
U20	25.0MHz	CLK25M	FPGA bank 65, pin AF19	available since PCB revision 02

Table 10: Reference clock signals

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anchor	Figure_3
title	Figure 3: TE0841-02 Power Distribution Diagram

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See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

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Table 14: Module PL I/O bank voltages

Board to Board Connector

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	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors

Variants Currently In Production

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Variants Currently In Production

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	-0.3	6.0	V	EN63A0QI, TPS74401RGW datasheets
3.3VIN supply voltage	-0.1	3.4	V	Xilinx datasheet DS892 (HR Bank VCCO)
VBAT_IN	-0.3	6.0	V	TPS780xx datasheet
Supply voltage for HR I/O banks (VCCO)	-0.500	3.400	V	Xilinx datasheet DS892
Supply voltage for HP I/O banks (VCCO)	-0.500	2.000	V	Xilinx datasheet DS892
I/O input voltage for HR I/O banks	-0.400	VCCO + 0.550	V	Xilinx datasheet DS892
I/O input voltage for HP I/O banks	-0.550	VCCO + 0.550	V	Xilinx datasheet DS892
I/O input voltage for SC CPLD U18	-0.5	3.75	V	LCMXO2-256HC datasheet
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)	-0.	GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)	-0.500	1.320	V	Xilinx datasheet DS892
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.500	1.260	V	Xilinx datasheet DS892
Storage temperature	-40	+100	°C	SML-P11 LED datasheet

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.3	5.5	V	TPS82085SIL, TPS74401RGW datasheet
3.3VIN supply voltage	3.3	3.4	V	Xilinx datasheet DS892 (HR Bank VCCO)
VBAT_IN	2.2	5.5	V	TPS780xx datasheet
Supply voltage for HR I/O banks (VCCO)	1.140	3.400	V	Xilinx datasheet DS892
Supply voltage for HP I/O banks (VCCO)	0.950	1.890	V	Xilinx datasheet DS892
I/O input voltage for HR I/O banks	–0.200	VCCO + 0.20	V	Xilinx datasheet DS892
I/O input voltage for HP I/O banks	–0.200	VCCO + 0.20	V	Xilinx datasheet DS892
I/O input voltage for SC CPLD U18	-0.3	3.6	V	LCMXO2-256HC datasheet
Industrial Module Operating Temperature Range	-40	85	°C	Xilinx datasheet DS892
Commercial Module Operating Temperature Range	0	85	°C	Xilinx DS892, Silicon Labs Si5338 datasheet

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Table 18: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

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Document Change History

Jul 2018 Mar 2018

Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
dateFormat	yyyy-MM-dd
type	Flat

update oscillator section with additional CLK

v.71

John Hartfiel

correction delivery section
update key features, document history

2018-08-07

v.69

Ali Naseri

updated pictures main components

2018-07-13

v.68

Ali Naseri

PCB REV02

2018-07-10

v.58

John Hartfiel

update links

2018-03-13

v.57

Jan Kumann, Ali Naseri

Initial document.

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all

Page info

infoType	Modified users
dateFormat	yyyy-MM-dd
type	Flat

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Table 18: Document change history.

Disclaimer

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	IN:Legal Notices
	IN:Legal Notices

02 Sept 2017

Trenz Electronic Documentation

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Old Version 63

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Variants Currently In Production

Variants Currently In Production

Document Change History

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