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Designate all graphics and pictures with a number and a description. For example "Figure 1: TE07xx-xx Block Diagram" or "Table 1: Initial delivery state". "Figure x" and "Table x" have to be formatted to bold.  

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Table of Contents


The Trenz Electronic TE0841-02 is an industrial-grade 4 x 5 cm SoM integrating Xilinx Kintex UltraScale FPGA, 2 GByte of DDR4 SDRAM, 64 MByte QSPI Flash for configuration and operation and powerful switch-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. All this on a tiny footprint, smaller than a credit card size at very competitive price. All Trenz Electronic 4 x 5 cm SoMs are mechanically compatible.

Use short link the Wiki Ressource page: for example:
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Refer to http://trenz.org/te0841-info for the current online version of this manual and other available documentation.

Key Features

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

  1. Xilinx Kintex UltraScale FPGA, U1
  2. Ultra performance oscillator @25.000000 MHz, U3
  3. 12A PowerSoC DC-DC converter (0.95V), U14
  4. 12A PowerSoC DC-DC converter (0.95V), U7
  5. Low-jitter precision LVDS oscillator @200.0000 MHz, U11

  6. Low-dropout (LDO) linear regulator (MGTAVTT 1.20V), U8
  7. Low-dropout (LDO) linear regulator (MGTAVCC 1.02V), U12
  8. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  9. Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  10. Samtec Razor Beam™ LSHM-130 B2B connector, JM3
  11. Programmable quad clock generator, U2
  12. 64 MByte QSPI Flash, U6
  13. 8 Gbit DDR4 SDRAM, U4
  14. 8 Gbit DDR4 SDRAM, U5
  15. System Controller CPLD, U18Programmable Clock Generator
  16. Low-dropout (LDO) linear regulator (MGTAUX), U9
  17. Ultra-low power low-dropout (LDO) regulator (VBATT), U19

Initial Delivery State

Storage device name



System Controller CPLD

Default firmware-
OTP Flash areaEmptyNot programmed
Quad clock generator OTP areaprogrammedon PCB REV02 and newer

Table 1: TE0841-02 module initial delivery state of programmable on-board devices

Boot Process

By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

Connections and Interfaces or B2B Pin's which are accessible by User

Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

FPGA BankTypeB2B ConnectorI/O Signal CountBank VCCO VoltageNotes
64HRJM148 IO's, 24 LVDS pairsB64_VCCOSupplied by the carrier board
65HRJM18 IO's3.3VOn-module power supply
65HRJM34 IO's3.3VOn-module power supply
66HPJM316 IO's, 8 LVDS pairsB66_VCCOSupplied by the carrier board
67HPJM248 IO's, 24 LVDS pairsB67_VCCOSupplied by the carrier board
67HPJM22 IO'sB67_VCCOSupplied by the carrier board
68HPJM218 IO's, 9 LVDS pairsB68_VCCOSupplied by the carrier board

Table 2: General overview of FPGA's PL I/O signals connected to the B2B connectors

For detailed information about the pin out, please refer to the Pin-out Tables.

TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.

MGT Lanes

MGT lanes should be listed separately, as they are more specific than just general I/Os.  

MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

LaneBankTypeSignal NameB2B PinFPGA Pin
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9
  • MGTHRXP0_225, Y2
  • MGTHRXN0_225, Y1
  • MGTHTXP0_225, AA4
  • MGTHTXN0_225, AA3
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15
  • MGTHRXP1_225, V2
  • MGTHRXN1_225, V1
  • MGTHTXP1_225, W4
  • MGTHTXN1_225, W3
  • MGT_RX2_P
  • MGT_RX2_N
  • MGT_TX2_P
  • MGT_TX2_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21
  • MGTHRXP2_225, T2
  • MGTHRXN2_225, T1
  • MGTHTXP2_225, U4
  • MGTHTXN2_225, U3
  • MGT_RX3_P
  • MGT_RX3_N
  • MGT_TX3_P
  • MGT_TX3_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27
  • MGTHRXP3_225, P2
  • MGTHRXN3_225, P1
  • MGTHTXP3_225, R4
  • MGTHTXN3_225, R3
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • JM1-12
  • JM1-10
  • JM1-6
  • JM1-4
  • MGTHRXP0_224, AH2
  • MGTHRXN0_224, AH1
  • MGTHTXP0_224, AG4
  • MGTHTXN0_224, AG3
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • JM1-24
  • JM1-22
  • JM1-18
  • JM1-16
  • MGTHRXP1_224, AF2
  • MGTHRXN1_224, AF1
  • MGTHTXP1_224, AF6
  • MGTHTXN1_224, AF5
  • MGT_RX6_P
  • MGT_RX6_N
  • MGT_TX6_P
  • MGT_TX6_N
  • JM1-27
  • JM1-25
  • JM1-19
  • JM1-17
  • MGTHRXP2_224, AD2
  • MGTHRXN2_224, AD1
  • MGTHTXP2_224, AE4
  • MGTHTXN2_224, AE3
  • MGT_RX7_P
  • MGT_RX7_N
  • MGT_TX7_P
  • MGT_TX7_N
  • JM3-2
  • JM3-4
  • JM3-1
  • JM3-3
  • MGTHRXP3_224, AB2
  • MGTHRXN3_224, AB1
  • MGTHTXP3_224, AC4
  • MGTHTXN3_224, AC3

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Clock signalBankSourceFPGA PinNotes
MGT_CLK0_P225B2B, JM3-33MGTREFCLK0P_225, Y6Supplied by the carrier board.
MGT_CLK1_P225U2, CLK1BMGTREFCLK1P_225, V6On-board Si5338A.
MGT_CLK2_P224B2B, JM3-34MGTREFCLK2P_224, AD6Supplied by the carrier board.
MGT_CLK3_P224U2, CLK2BMGTREFCLK3P_224, AB6On-board Si5338A.

Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Kintex UltraScale FPGA is available through B2B connector JM2.

JTAG Signal

B2B Connector Pin


Table 5: JTAG interface signals

JTAGMODE pin 89 in B2B connector JM1 should be set low or grounded for normal operation. Set this pin high for SC CPLD update via JTAG interface.

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Pin NameSC CPLD DirectionFunctionDefault Configuration
JTAGMODEInputJTAG selectLow for normal operation.
nRST_SC0InputResetLow active board reset input
SC1--not currently used ('BOOTMODE' in default B2B pin out')
SC2Input / Output-Power good signal ('PGOOD' in default B2B pin out)
SC3Input-Power enable pin ('EN1' in default B2B pin out)
SC4--not currently used ('NOSEQ' in default B2B pin out')

JTAG signals between

B2B JTAG signals are forwarded to the FPGA through SC CPLD.
TCKInputJTAG signals between
SC CPLD and B2B connector

Program FPGA or SC CPLD depending on pin JTAGMODE.

PROG_BOutputFPGA configurationPL configuration reset signal.
DONEInputFPGA configuration donePL configuration completed.
PUDC_BOutputPull up during configuration

PL I/O's are 3-stated until configuration of the FPGA completes.

INIT_BInputInitialization done

Low active FPGA initialization pin or configuration error signal.

EN_PLInputEnable PL Power DC-DC convertersSet to contant logical high.
CPLD_IOOutputuser I/OConnected to FPGA Bank 45, pin P28.

Table 6: System Controller CPLD I/O pins

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.

For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
Add link to the Wiki reference page of the SC CPLD, if available.

Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

Signal NameQSPI Flash Memory U6 PinFPGA Pin
SPI_D1D2D01_DIN_0, Y7
SPI_D2C4D02_0, U7
SPI_D3D4D03_0, V7

Table 7: Quad SPI interface signals and connections

I2C Interface

On-module I²C interface is routed  from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

I²C InterfaceSchematic net namesConnected toI²C AddressNotes
PL bank 65 I/O

'PLL_SCL', pin AB20

'PLL_SDA' pin AB19

Si5338 U2, pin 12

Si5338 U2, pin 19

0x70default address
PL bank 65 I/O

'B65_SCL', pin Y19

'B65_SDA', pin AA19

B2B JM1, pin 95

B2B JM1, pin 93


Table 8: I2C slave device addresses

On-board Peripherals

Components on the Module, like Flash, PLL, PHY...

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

Put in link to the Wiki reference page of the firmware of the SC CPLD.

DDR Memory

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Programmable Clock Generator

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

Si5338A Pin
Signal Name / Description
Connected toDirectionNote



not connectedInput

not used

IN2-GNDInputnot used


Reference input clock

U3, pin 3Input25.000000 MHz oscillator, Si8208AI


-GNDInputI2C slave device address LSB.



not connectedInputnot used
IN6-GNDInputnot used



U1, R23Output

FPGA bank 45, default 100MHz*


FPGA MGT bank 225 reference clock, default 125MHz*

CLK2AMGT_CLK3_NU1, AB5OutputFPGA MGT bank 224 reference clock, default 156,25MHz*


U1, pin T24Output

FPGA bank 45, default 156,25MHz*

CLK3BCLK0_NU1, pin T25

 Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed


The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock SourceFrequencySignal NameClock DestinationNotes
U3, SiT8208AI25.000000 MHzCLKSi5338A PLL U2, pin 3 (IN3)-
U11, DSC1123DL5200.0000 MHzCLK200M_PFPGA bank 45, pin R25

Enable by FPGA bank 65, pin AF24

Signal: 'ENOSC'

CLK200M_NFPGA bank 45, pin R26

Table 10: Reference clock signals

On-board LEDs

LEDColorConnected toDescription and Notes
D1GreenSystem Controller CPLD, bank 3Exact function is defined by SC CPLD firmware.

Table 11: On-board LEDs

Power and Power-On Sequence

If power sequencing and distribution is not so much, you can join both sub sections together

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power InputTypical Current

Table 12: Typical power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

Power-On Sequence

The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power Rails

Power Rail Name

B2B JM1 Pins

B2B JM2 Pins


VIN1, 3, 52, 4, 6, 8InputSupply voltage.
3.3VIN13, 15-InputSupply voltage.
B64_VCO9, 11-InputHR (High Range) bank voltage.
B66_VCO-1, 3InputHP (High Performance) bank voltage.
B67_VCO-7, 9InputHP (High Performance) bank voltage.
B68_VCO-5InputHP (High Performance) bank voltage.


79-InputRTC battery supply voltage.
3.3V-10, 12, 91OutputModule on-board 3.3V voltage level.

Table 13: Module power rails

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Bank Voltages


Schematic Name


Voltage Range

0 (config)



44 HPDDR_1V21.2VHP: 1.2V to 1.8V
45 HPPL_1.8V1.8VHP: 1.2V to 1.8V
46 HPDDR_1V21.2VHP: 1.2V to 1.8V
64 HRB64_VCOuserHR: 1.2V to 3.3V
65 HR3.3V3.3VHR: 1.2V to 3.3V
66 HPB66_VCOuserHP: 1.2V to 1.8V
67 HPB67_VCOuserHP: 1.2V to 1.8V
68 HPB68_VCOuserHP: 1.2V to 1.8V

Table 14: Module PL I/O bank voltages

Board to Board Connector

Variants Currently In Production

Set correct link to the overview table of the product on english and german, if not available, set 

See also the current available variants on the Trenz Electronic shop page

Trenz shop TE0841 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings




Reference Document

VIN supply voltage



EN63A0QI, TPS74401RGW datasheets
3.3VIN supply voltage-0.13.4VXilinx datasheet DS892 (HR Bank VCCO)
VBAT_IN-0.36.0VTPS780xx datasheet
Supply voltage for HR I/O banks (VCCO)



VXilinx datasheet DS892

Supply voltage for HP I/O banks (VCCO)


2.000VXilinx datasheet DS892
I/O input voltage for HR I/O banks


VCCO + 0.550

VXilinx datasheet DS892

I/O input voltage for HP I/O banks


VCCO + 0.550

VXilinx datasheet DS892
I/O input voltage for SC CPLD U18-0.53.75VLCMXO2-256HC datasheet
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2)-0.5001.320VXilinx datasheet DS892

GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage



VXilinx datasheet DS892

Storage temperature




SML-P11 LED datasheet

Table 16: Module absolute maximum ratings

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage3.35.5VTPS82085SIL, TPS74401RGW datasheet
3.3VIN supply voltage3.33.4VXilinx datasheet DS892 (HR Bank VCCO)
VBAT_IN2.25.5VTPS780xx datasheet
Supply voltage for HR I/O banks (VCCO)1.140


VXilinx datasheet DS892

Supply voltage for HP I/O banks (VCCO)



VXilinx datasheet DS892

I/O input voltage for HR I/O banks


VCCO + 0.20VXilinx datasheet DS892
I/O input voltage for HP I/O banks–0.200VCCO + 0.20VXilinx datasheet DS892
I/O input voltage for SC CPLD U18-0.33.6VLCMXO2-256HC datasheet

Industrial Module Operating Temperature Range

-4085°CXilinx datasheet DS892
Commercial Module Operating Temperature Range085°CXilinx DS892, Silicon Labs Si5338 datasheet

Table 17: Module recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Please check also Xilinx datasheet DS892 for complete list of absolute maximum and recommended operating ratings.

Physical Dimensions

All dimensions are given in millimeters.


Revision History

Hardware Revision History



PCNDocumentation Link
2018-05-1102current available board revisionPCN-20180511TE0841-02


First production release


Table 18: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.





  • correction delivery section
  • update key features, document history
2018-08-07v.69Ali Naseri
  • updated pictures main components
2018-07-13v.68Ali Naseri
  • PCB REV02



John Hartfiel
  • update links


v.57Jan Kumann, Ali Naseri
  • Initial document.

  • --

Table 18: Document change history