Page History

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

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Overview

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Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Key Features

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Excerpt
QSPI SDK Custom Carrier (minimum PS Design with available module components only) Special FSBL for QSPI Programming

Revision History

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new assembly variant

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rework Board Part Files

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Update Board Part CSV File with new Flash assembly variants

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2017-11-14

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Initial release

Release Notes and Know Issues

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Requirements

Software

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Hardware

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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design. * Only different Flash size.

Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Description

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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

TE0803 "Test Board" Reference Design

Design Flow

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Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Programming

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Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

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Connect JTAG and power on PCB
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correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

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Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

Usage

QSPI Boot:

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

Debugging:

System Design - Vivado

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Block Design

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PS Interfaces

Activated interfaces:

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Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2017.4 FSBL

Changes:

Set FSBL Boot Mode to JTAG
Disable Memory initialisation

Hello TE0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

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No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Date	Version	Changes	Author
2024-06-18	3.1.18	Design flow → point 6 changed: the file boot.scr ... changed from required to optional	ma
2023-12-14	3.1.17	updated according to Vivado 2023.2	ma
2023-06-13	3.1.16	Design flow: added alternative programming files in Petalinux added chapter FSBL Patch in Software Design - Petalinux	ma
2023-06-01	3.1.15	removed u-boot.dtb from Design flow	ma
2023-06-01	3.1.14	expandable lists for revision history and supported hardware	wh
2023-05-25	3.1.13	updated according to Vivado 2022.2	ma
2023-02-08	3.1.12	removed content of Special FSBL for QSPI programming	ma
2022-08-24	3.1.11	Modification from link "available short link"	ma
2022-01-25	3.1.10	removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin corrected Boot Source File in Boot Script-File	ma
2022-01-14	3.1.9	extended notes for microblaze boot process with linux add u.boot.dtb to petalinux notes add dtb to prebuilt content replace 20.2 with 21.2	jh
2021-06-28	3.1.8	added boot process for Microblaze minor typos, formatting	ma
2021-06-01	3.1.7	carrier reference note	jh
2021-05-04	3.1.6	removed zynq_ from zynq_fsbl	ma
2021-04-28	3.1.5	added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export minor typos, formatting	ma
2021-04-27	3.1.4	Version History changed from list to table Design flow removed step 5 from Design flow changed link from TE Board Part Files to Vivado Board Part Flow changed cmd shell from picture to codeblock added hidden template for "Copy PetaLinux build image files", depending from hardware added hidden template for "Power on PCB", depending from hardware Usage update of boot process Requirements - Hardware added "^*used as reference" for hardware requirements all placed a horizontal separation line under each chapter heading changed title-alignment for tables from left to center all tables added "<project folder>\board_files" in Vivado design sources	ma
	3.1.3	Design Flow formatting Launch formatting	ma
	3.1.2	minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.src description added USB for programming	ma
	3.1.1	swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow	ma
	3.1	Fix problem with pdf export and side scroll bar update 19.2 to 20.2 add prebuilt content option
	3.0	add fix table of content add table size as macro removed page initial creator

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Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
sortByColumn 1
sortEnabled false
cellHighlighting true
Example
Comment
1
2

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Overview

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

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Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/TI/Redirects

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

Key Features

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Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 2023.2 QSPI Custom Carrier (minimum PS Design with available module components only) Modified FSBL (some additional outputs only)

Revision History

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Notes :

add every update file on the download
add design changes on description

Expand

title	Expand List

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Date	Vivado	Project Built	Authors	Description
2024-08-28	2023.2	TE0803-test_board-vivado_2023.2-build_4_20240823075240.zip TE0803-test_board_noprebuilt-vivado_2023.2-build_4_20240823075240.zip	John Hartfiel	2023.2 update new assembly variants board files: fixed PS refc clk rounding issue
2023-09-14	2022.2	TE0803-test_board-vivado_2022.2-build_8_20230914124756.zip TE0803-test_board_noprebuilt-vivado_2022.2-build_8_20230914124756.zip	Manuela Strücker	2022.2 update new assembly variants
2022-10-17	2021.2.1	TE0803-test_board-vivado_2021.2-build_18_20221017093148.zip TE0803-test_board_noprebuilt-vivado_2021.2-build_18_20221017093148.zip	Manuela Strücker	script update
2022-08-30	2021.2.1	TE0803-test_board-vivado_2021.2-build_15_20220830131430.zip TE0803-test_board_noprebuilt-vivado_2021.2-build_15_20220830131430.zip	Manuela Strücker	new assembly variants
2022-04-05	2021.2	TE0803-test_board-vivado_2021.2-build_11_20220405100116.zip TE0803-test_board_noprebuilt-vivado_2021.2-build_11_20220405100116.zip	Manuela Strücker	2021.2 update
2021-09-06	2020.2	TE0803-test_board-vivado_2020.2-build_7_20210906104518.zip TE0803-test_board_noprebuilt-vivado_2020.2-build_7_20210906104536.zip	Manuela Strücker	2020.2 update update document style
2020-04-06	2019.2	TE0803-test_board-vivado_2019.2-build_9_20200406081019.zip TE0803-test_board_noprebuilt-vivado_2019.2-build_9_20200406081036.zip	John Hartfiel	new assembly variants
2020-03-25	2019.2	TE0803-test_board-vivado_2019.2-build_8_20200325082253.zip TE0803-test_board_noprebuilt-vivado_2019.2-build_8_20200325082311.zip	John Hartfiel	script update
2020-01-23	2019-2	TE0803-test_board-vivado_2019.2-build_3_20200123070036.zip TE0803-test_board_noprebuilt-vivado_2019.2-build_3_20200123070049.zip	John Hartfiel	2019.2 update Vitis support FSBL SI programming procedure update
2019-5-06	2018.3	TE0803-test_board_noprebuilt-vivado_2018.3-build_05_20190506161948.zip TE0803-test_board-vivado_2018.3-build_05_20190506161936.zip	John Hartfiel	custom FSBL new assembly variants
2018-10-26	2018.2	TE0803-test_board_noprebuilt-vivado_2018.2-build_03_20181026141705.zip TE0803-test_board-vivado_2018.2-build_03_20181026141651.zip	John Hartfiel	new assembly variant
2018-08-14	2018.2	TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip TE0803-test_board-vivado_2018.2-build_02_20180814103105.zip	John Hartfiel	new assembly variant
2018-07-13	2018.2	TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180713085721.zip TE0803-test_board-vivado_2018.2-build_02_20180713085704.zip	John Hartfiel	additional notes for FSBL generated with Win SDK changed *.bif
2018-05-17	2017.4	TE0803-test_board_noprebuilt-vivado_2017.4-build_09_20180517152118.zip TE0803-test_board-vivado_2017.4-build_09_20180517152103.zip	John Hartfiel	new assembly variant
2018-04-11	2017.4	TE0803-test_board_noprebuilt-vivado_2017.4-build_07_20180411081821.zip TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip	John Hartfiel	bugfix TE0803-01-04EG board part file
2018-02-13	2017.4	TE0803-test_board_noprebuilt-vivado_2017.4-build_06_20180213120257.zip TE0803-test_board-vivado_2017.4-build_06_20180213120229.zip	John Hartfiel	new assembly variant
2018-02-05	2017.4	TE0803-test_board-vivado_2017.4-build_05_20180205101915.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180205101943.zip	John Hartfiel	new assembly variant
2018-01-31	2017.4	TE0803-test_board-vivado_2017.4-build_05_20180131124202.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180131124215.zip	John Hartfiel	new assembly variant
2018-01-18	2017.4	TE0803-test_board-vivado_2017.4-build_05_20180118160549.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180118160604.zip	John Hartfiel	rework Board Part Files
2017-11-16	2017.2	TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip	John Hartfiel	Update Board Part CSV File with new Flash assembly variants
2017-11-14	2017.2	TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip	John Hartfiel	Initial release

Release Notes and Know Issues

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Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

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Issues	Description	Workaround	To be fixed version
Xilinx Software	Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request	use corresponding board files for the Vivado versions	--
QSPI Flash	Flash programming is not supported with boot mode QSPI or SD.	If flash programming fails, configure device for JTAG boot mode and try again or use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)	--

Requirements

Software

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Notes :

list of software which was used to generate the design

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Software	Version	Note
Vitis	2023.2	needed, Vivado is included into Vitis installation

Hardware

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Notes :

list of hardware which was used to generate the design
mark the module and carrier board, which was used tested with an ^*

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

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Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	EMMC	Others	Notes
TE0803-01-02CG-1E	2cg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-02CG-1EA	2cg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-02EG-1E	2eg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-02EG-1EA	2eg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-03CG-1E	3cg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-03CG-1EA	3cg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-03EG-1E	3eg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-03EG-1EA	3eg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-04CG-1EA	4cg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-04CG-1EB	4cg_2gb	REV01	2GB	256MB	NA	NA	NA
TE0803-01-04EG-1EA	4eg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-04EV-1E3	4ev_2gb	REV01	2GB	128MB	NA	1 mm connectors	NA
TE0803-01-05EV-1EA	5ev_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-05EV-1IA	5ev_i_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-02-03EG-1EB	3eg_4gb	REV02\|REV01	4GB	128MB	NA	NA	NA
TE0803-02-04EG-1E3	4eg_4gb	REV02	4GB	128MB	NA	1 mm connectors	NA
TE0803-02-04EV-1EA	4ev_2gb	REV02\|REV01	2GB	128MB	NA	NA	NA
TE0803-02-04EV-1E3	4ev_4gb	REV02	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-2AE11-A	2cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-2BE11-A	2eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-3AE11-A	3cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-3AE11-AK	3cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-3AE10-R	3cg_0_2gb	REV03	2GB	NA	NA	NA	PS MIO 3.3V, not compatible to trenz carrier
TE0803-03-3BE11-A	3eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-3BE21-A	3eg_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-3BE31-A	3eg_8gb	REV03	8GB	128MB	NA	NA	dual die ddr
TE0803-03-3BI21-A	3eg_i_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-3RI21-A	3eg_li_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-4AE11-A	4cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4BE11-A	4eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4BE21-L	4eg_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4BI21-A	4eg_i_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-4BI21-X	4eg_i_4gb	REV03	4GB	128MB	NA	NA	U41 replaced with diode
TE0803-03-4BI61-A	4eg_8gb	REV03	8GB	128MB	NA	NA	dual die ddr
TE0803-03-4BI61-X	4eg_8gb	REV03	8GB	128MB	NA	NA	dual die ddr
TE0803-03-4DE11-A	4ev_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4DE21-L	4ev_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4DE21-LZ	4ev_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4DI21-D	4ev_i_4gb	REV03	4GB	128MB	NA		NA
TE0803-03-4DI21-L	4ev_i_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4GE11-A	4eg_2_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4GE21-L	4eg_2_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4GI11-A	4eg_2i_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4GI21-A	4eg_2i_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-5BE11-A	5eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-5DE11-A	5ev_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-5DI21-A	5ev_i_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-5DI24-A	5ev_i_4gb	REV03	4GB	512MB	NA	NA	NA
TE0803-03-S003	4ev_2gb	REV03	2GB	128MB	NA	NA	CAO: TE0803-03-4DE11-A
TE0803-03-S005	4eg_2gb	REV03	2GB	128MB	NA	NA	CAO: TE0803-03-4BI1?-A
TE0803-04-2AE11-A	2cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-2BE11-A	2eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-2BE11-AK	2eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-3AE10-R	3cg_0_2gb	REV04	2GB	NA	NA	NA	PS MIO 3.3V, not compatible to trenz carrier
TE0803-04-3AE11-A	3cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-3AE11-AK	3cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-3BE11-A	3eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-3BE21-A	3eg_4gb	REV04	4GB	128MB	NA	NA	NA
TE0803-04-3BE21-L	3eg_4gb	REV04	4GB	128MB	NA	NA	NA
TE0803-04-4AE11-A	4cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4AE11-AK	4cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4AE11-AZ	4cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4BE11-A	4eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4BE11-AK	4eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4BE21-L	4eg_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-4BI21-A	4eg_i_4gb	REV04	4GB	128MB	NA	NA	NA
TE0803-04-4BI21-X	4eg_i_4gb	REV04	4GB	128MB	NA	NA	U41 replaced with diode
TE0803-04-4BI61-A	4eg_8gb	REV04	8GB	128MB	NA	NA	dual die ddr
TE0803-04-4BI61-X	4eg_8gb	REV04	8GB	128MB	NA	NA	dual die ddr
TE0803-04-4DE11-A	4ev_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4DE11-AK	4ev_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4DE11-AZ	4ev_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-4DE21-L	4ev_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-4DE21-LZ	4ev_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-4DI21-D	4ev_i_4gb	REV04	4GB	128MB	NA		NA
TE0803-04-4DI21-L	4ev_i_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-4GE21-L	4eg_2_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-4GE81-L	4eg_2_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-4GI21-A	4eg_2i_4gb	REV04	4GB	128MB	NA	NA	NA
TE0803-04-5BE11-A	5eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-5DE11-A	5ev_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-5DI21-A	5ev_i_4gb	REV04	4GB	128MB	NA	NA	NA
TE0803-04-S006	4ev_4gb	REV04	4GB	128MB	NA	1 mm connectors	CAO: TE0803-04-4DE21-L
TE0803-04-S009	4eg_2_4gb	REV04	4GB	128MB	NA	1 mm connectors	CAO: TE0803-04-4GE21-L
TE0803-04-S010	5ev_2gb	REV04	2GB	128MB	NA	NA	CAO: TE0803-04-5DE11-A
TE0803-04-S011	4eg_2_4gb	REV04	4GB	64MB	NA	1 mm connectors	CAO: TE0803-04-4GE25-L
TE0803-04-S012	2cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-S013	3cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-S014	4eg_2_4gb	REV04	4GB	64MB	NA	1 mm connectors	CAO: TE0803-04-4GE2?-LZ
TE0803-04-S016	4cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-S017	2eg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-S018	4eg_2_4gb	REV04	4GB	128MB	NA	1 mm connectors	NA
TE0803-04-S020	4cg_2gb	REV04	2GB	128MB	NA	NA	NA
TE0803-04-S022	4eg_2_4gb	REV04	4GB	128MB	NA	1 mm connectors	CAO: TE0803-04-4GE21-LZ
TE0803-04-S023	4eg_2_4gb	REV04	4GB	128MB	NA	1 mm connectors	CAO: TE0803-04-4GE81-L
TE0803-04-S026	5ev_i_4gb	REV04	4GB	128MB	NA	NA	CAO: TE0803-04-5DI21-A
TE0803-04-S027	3cg_2gb	REV04	2GB	128MB	NA	NA	CAO:TE0803-04-3AE11-A

^*used as reference

Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this board part files are not used for this reference design.

Design supports following carriers:

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Carrier Model	Notes
Custom PCB	use simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808^*	Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended
TEBT0808-01	Change UART0 to UART1 (MIO68...69) and regenerate design

^*used as reference

Additional HW Requirements:

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Additional Hardware	Notes
---	---

^*used as reference

Content

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Notes :

content of the zip file

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

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Type	Location	Notes
Vivado	<project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files	Vivado Project will be generated by TE Scripts
Vitis	<project folder>\sw_lib	Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation

Additional Sources

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Type	Location	Notes
---	---	---

Prebuilt

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Notes :

prebuilt files

Template Table:

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Device Tree	*.dts	Device tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0803 "Test Board" Reference Design

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

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Note:

Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select create and open delivery binary folder
  Info
  Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block
language py
theme Midnight
title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
TE::pr_program_flash -swapp hello_te0803

SD-Boot mode

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with Vitis Debugger into device

Usage

QSPI Boot:

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info
Note: See TRM of the Carrier, which is used.
Power On PCB
Expand
title boot process
1. ZynqMP Boot ROM loads FSBL from QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR,

System Design - Vivado

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Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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title	Block Design

Image Added

PS Interfaces

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Note:

optional for Zynq / ZynqMP only
add basic PS configuration

Activated interfaces:

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Type	Note
DDR
QSPI	MIO
UART0	MIO, please select other one, if you have connected UART to second controller or other MIO
SWDT0..1
TTC0..3

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - Vitis

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Note:

optional chapter separate
sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2023.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

hello_te0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

No additional software is needed.

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
type	Flat

Release 2023.2
new assembly variants

2023-09-14

v.34

Manuela Strücker

Release 2023.2
new assembly variants

2022-10-17

v.33

Manuela Strücker

script update

2022-09-06

v.32

Manuela Strücker

new assembly variants

2022-07-15

v.30

Manuela Strücker

Release 2021.2

2021-09-09

v.25

Manuela Strücker

Release 2020.2

2020-04-06

v.24

John Hartfiel

new assembly variants

2020-03-25

v.23

John Hartfiel

Script update

2020-01-23

v.22

John Hartfiel

Release 2019.2

2019-05-07

v.21

John Hartfiel

Release 2018.3

2018-10-26

v.18

John Hartfiel

new assembly variant

2018-08-14

v.16

John Hartfiel

new assembly variant

2018-07-13

v.15

John Hartfiel

Release 2018.2

2018-05-18

v.14

John Hartfiel

new assembly variant

2018-04-11

v.13

John Hartfiel

bugfix board part file

2018-04-03

v.11

John Hartfiel

...

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 7

New Version Current

Key

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

QSPI

SD

JTAG

Usage

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

zynqmp_fsbl

zynqmp_fsbl_flash

Hello TE0803

Additional Software

Appx. A: Change History and Legal Notices

Document Change History

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI-Boot mode

SD-Boot mode

JTAG

Usage

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

fsbl

zynqmp_fsbl

zynqmp_pmufw

hello_te0820

u-boot

zynqmp_fsbl

hello_te0803

Additional Software

Appx. A: Change History and Legal Notices