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Note

The usage of this steps is at owner's own risk. Trenz Electronic is not liable for damage caused by following this steps.

Short Description

The TE0722 is configured to boot from flash with JTAG in cascade mode. If you configure the TE0722 Flash with wrong Boot.bin (for ex. you use Xilinx default or wrong FSBL. Or you insert additional applications file into the boot.bin without necessary workarounds), the Zynq - PS is running into a state, in which the FPGA and the Flash is not accessible via JTAG.This workaround set the FPGA in JTAG independent mode on startup to erase the corrupt flash content.

TE0722 does boot always from SPI Flash, changing the Boot Mode is not possible from any of the accessible connector or switches.

If TE0722 SPI Flash is accidentally programmed with Boot.bin that includes a FSBL that is not adapter for TE0722 DDR-less operation then ZYNQ Boot-ROM will not release JTAG DAP, and access to JTAG including reprogramming the SPI Flash is no longer possible.

 

Note
Note

The Xilinx tools do not handle DDR-Less Design FSBL autogeneration correctly, to . To get around this "bug" problem manual modifications are necessary, see DDR less ZYNQ Design. It should be fixed or make a little bit confortable by Xilinx but until Vivado 2016.2 it's not done.

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Procedure

For this case, you can try the following steps without guarantee for success:

  1. Close all Xilinx Programs.
  2. Power off TE0722
  3. Bridge S25FL127S Pin 7 temporary with GND to set change Boot Mode  Mode to JTAG Bode Boot Mode only (See picture).
  4. Power on TE0722
  5. Open SDK
  6. Disconnect you the GND bridge to wire from Pin 7
  7. (optional) Try to get access to the FPGA with SDK Debugger (Is this not possible, flash programming is also not possible)
  8. Open SDK
  9. Program Try to program Flash with valid Boot.Bin, if programming failed try again from step 1.

GND-Bridge to S25FL127S Pin 7

Changing bootmode

The easiest way to change the Boot Mode pinstrap is temporary connection of SPI Flash Pin 7 to ground. This pin Pin 7 is connected with Pullup-Resistor to 3.3V, to set FPGA in Quad-SPI Mode. To short Shorting this Pin with GND will enable JTAG Bode Boot Mode only.

Connect Pin 7 to one of the GND Pins only temporary for startup procedure(Temporary during powerup). After startup, Pin 7 trace is used to program the Flash. So you must disconnect your GND-bridge, so it must be floated (disconnected from ground).

 

 

References

  • Zynq-7000 All Programmable SoC - Technical Reference Manual (UG585):Page 167-Section 6.25 Boot Mode Pin Settings
  • TE0722 Schematics:TE0722 Download Page

 

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