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Template Revision 2.6

Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default style
widths sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

Intel® MAX 10 Commercial [10M08SAU169C8G]
- Package:
  UBGA
  UBGA-169
- Speed Grade: C8 (Slowest)
- Temperature: 0°C
  ~
  to 85°C
- Package compatible device
  10M02
  10M08...10M16 as assembly variant on request possible
SDRAM Memory up to
64Mb, 166MHz
32 Mbyte (8Mbyte default)
USB 2.0
Dual High Speed USB to
Multipurpose UART/FIFO IC
Quad SPI Flash, 64Mb
(FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
SPI Flash - NOT INSTALLED (only special option)
EEPROM Memory, 4Kb
8x User LED Micro USB2 Receptacle 90
18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface:
- 250x GPIO
- 116x LVDS
23x GPIO - Arduino MKR compatible
Power Supply:
5V
Dimension: 86.5mm x 25mm
Others:
- Instrumentation Amplifier
- Differential Amplifier
- Operational Amplifier

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

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Scroll Title

anchor	Figure_OV_BD
title	TEI0015 block diagram

Scroll Ignore

draw.io Diagram

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Scroll Only

Main Components

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Scroll Title

anchor	Figure_OV_BD
title	TEI0015 main components

Scroll Ignore

draw.io Diagram

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Scroll Only

SMA Connector, J5...6
Amplifier, U12 - U14 - U6
Series
Voltage Reference, U8
Analog to Digital
Convertor
Converter, U15
Voltage Regulator, U10 - U13 - U16
Switching Voltage Regulator/LDO, U11 - U4
SDRAM Memory, U2
Intel® MAX 10 FPGA, U1SDRAM Memory, U2
SPI Flash Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
4Kb
FTDI configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro
USB2 Receptacle
USB Connector, J9
1x14 pin header

, J2 (Not assembled)
, J2
1x6 pin header

, J4 (Not assembled)
, J4
Jumper
1x4 Header, J3 (Not assembled)
1x14 pin header

, J1 (Not assembled)
, J1

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Scroll Title

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

style

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sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
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SDRAM

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

EEPROM

Programmed

FTDI configuration

Not Programmed

Configuration Signals

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id	Comments

Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

Scroll Title

anchor	Table_OV_RST
title	Reset process.

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widths

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Signal	Push Button	Pin Header	Note
RESET	S1	J2	connected Connected to nCONFIG

Signals, Interfaces and Pins

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Scroll Title

anchor	Table_SIP_GIOs
title	General I/Os to Pin Headers and connectors information

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style

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FPGA Bank	Connector Designator	I/O Signal Count	Voltage Level	Notes
Bank 1A	J1	7	3.3V	AIN0...6
Bank 1B	J4	5	3.3V	JTAG interface
Bank 2	J1	4	3.3V	DIO2...5
Bank 5	J2	9	3.3V	DIO6...14
Bank 5	J1	2	3.3V	DIO0...1
Bank 8	J2	1	3.3V	RESET

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Scroll Title

anchor	Table_OBP_IOs
title	FPGA I/O Banks

FPGA Bank	I/O Signal Count	Connected to	Notes
Bank 1A	7	1x14 Pin header, J1	AIN0...6
Bank 1A	1	Jumper, J3	AIN7
Bank 1B	5	1x6 Pin header, J4	JTAG_EN, TDI, TDO, TMS, TCK
Bank 2	4	1x14 Pin header, J1	D2...5
	5	A2D, U15	ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
	1	12MHz Oscillator, U7	CLK12M
	2	Amplifier, U12	nIAMP_A0, nIAMP_A1
Bank 3	22	SDRAM, U2	RAM_ADDR_CMD
Bank 5	9	1x14 Pin header, J2	DIO6...14
	2	1x14 Pin header, J1	DIO0...1
	1	D12_R	DIO12
Bank 6	16	SDRAM, U2	DQ0...15
	2	SDRAM, U2	DQM0...1
	1	D11_R	DIO11
Bank 8	8	User Red LEDs, D2...9	LED0...7
	6	SPI Flash, U5	F_CS, F_CKCKL, F_DI, F_DO, nSTATUS, DEVCLRn
	1	Red LED, D10	CONF_DONE
	6	FTDI JTAG/UART Adapter, U3	BDBUS0...5
	1	Push Button, S2	USER_BTN

Micro

...

-USB Connector

The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.

Scroll Title

anchor	Table_OBP_USB
title	Micro USB-2 connector pins

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
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It is connected to GND

Pins	Connected to	Note
VBUS	USB_VBUS
D+	FTDI FT2232H U3, DP pin
D-	FTDI FT2232H U3, DM pin

JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

Scroll Title

anchor	Table_SIP_JTG
title	JTAG pins connection

Scroll Table Layout

widths

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JTAG Signal	Pin Header Connector	Note
TMS	J4-6
TDI	J4-5
TDO	J4-4
TCK	J4-3
JTAG_EN	J4-2	Pulled-up to 3.3V

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

...

Scroll Title

anchor	Table_OBP
title	On board peripherals

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Chip/Interface	Designator	Notes

SDRAM

77530153	U2
FTDI FT2232H	U3	JTAG/UART

Adapter

/FIFO

SPI Flash

Memory

U5

EEPROM


77530153	U9
Oscillator	U7

12MHz

12 MHz clock source

ADC

77530153

U12, U14

Analog to Digital

Convertor

Converter
Push Buttons	S1...2
8x User LEDs	D2...9	Red LEDs

SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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Scroll Title

anchor	Table_OBP_SDRAM
title	SDRAM interface IOs and pins

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repeatTableHeaders	default	style
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SDRAM I/O Signals	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank 3	-
Bank address inputs	BA0 / BA1	bank 3	-
Data input/output	DQ0 ... DQ15	bank 6	-
Data mask	DQM0 ... DQM1	bank 6	-
Clock	CLK	bank 3	-
Control Signals	CS	bank 3	Chip select
	CKE	bank 3	Clock enable
	RAS	bank 3	Row Address Strobe
	CAS	bank 3	Column Address Strobe
	WE	bank 3	Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

Scroll Title

anchor	Table_OBP_FTDI
title	FTDI chip interfaces and pins

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repeatTableHeaders	default	style
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FTDI Chip U3 Pin	Signal Schematic Name	Connected to	Notes
ADBUS0	TCK	FPGA bank 1B, pin G2	JTAG interface
ADBUS1	TDI	FPGA bank 1B, pin F5
ADBUS2	TDO	FPGA bank 1B, pin F6
ADBUS3	TMS	FPGA bank 1B, pin G1
BDBUS0	BDBUS0	FPGA bank 8, pin A4	user User configurable
BDBUS1	BDBUS1	FPGA bank 8, pin B4	user User configurable
BDBUS2	BDBUS2	FPGA bank 8, pin B5	user User configurable
BDBUS3	BDBUS3	FPGA bank 8, pin A6	user User configurable
BDBUS4	BDBUS4	FPGA bank 8, pin B6	user User configurable
BDBUS5	BDBUS5	FPGA bank 8, pin A7	user User configurable
BDBUS6

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

...

anchor	Table_OBP_QSPI
title	Quad SPI Flash memory interface

...

FPGA bank 8, pin C4

...

BDBUS6	FPGA bank 6, pin C11
BDBUS7	BDBUS7	FPGA bank 3, pin J7
BCBUS0	BCBUS0	FPGA bank 5, pin J9
BCBUS1	BCBUS1	FPGA bank 3, pin K5
BCBUS2	BCBUS2	FPGA bank 3, pin L4
BCBUS3	BCBUS3	FPGA bank 3, pin L5
BCBUS4	BCBUS4	FPGA bank 3, pin N12

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

Scroll Title

anchor	Table_OBP_QSPI
title	Quad SPI Flash memory interface

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Scroll Title

anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

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Signal Schematic Name	Connected to	Notes
F_CS	FPGA bank 8, pin B3	Chip select
F_CLK	FPGA bank 8, pin A3	Clock
F_DI	FPGA bank 8, pin A2	Data in / out
nSTATUS	FPGA bank 8, pin C4	Data in / out, configuration dual-purpose pin of FPGA
DEVCLRN	FPGA bank 8, pin B9	Data in / out, configuration dual-purpose pin of FPGA
F_DO	FPGA bank 8, pin B2	Data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.

Scroll Title

anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

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Schematic	Connected to	Notes
EECS	FTDI U3, Pin EECS
EECLK	FTDI U3, Pin EECLK
EEDATA	EECS	FTDI U3, Pin EECS	EECLK	FTDI U3, Pin EECLK	EEDATA	FTDI U3, Pin EEDATA

ADC

The TEI0015 board is equipped with the 18the Analog Devices AD4003BCPZ-RL7 18-bit 2MSPS ADC provided by Analog Devices, .

Scroll Title

anchor	Table_OBP_A2D
title	A2D converter interface and pins

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Pins	Connected to	Notes
IN+	Diff Amplifier U14, VOUT-
IN-	Diff Amplifier U14, VOUT+
SDI	Bank FPGA, bank 2, pin M2, ADC_SDI
SDOBank	2, ADCFPGA, bank 2, pin M1, ADC_SDO
SCKBank	2, ADCFPGA, bank 2, pin N3, ADC_SCK
CNV	Bank FPGA, bank 2, pin N2, ADC_CNV

LEDs

Scroll Title

anchor	Table_OBP_LED
title	On-board LEDs

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style

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Designator	Color	Connected to	Active Level	Note
D2...9	Red	LED1...8	Active High	User LEDs
D10	Red	CONF_DONE	Active Low	Configuration DONE LED
D1	Green	3.3V	Active High	After power on it will be on.

Push Bottuns

Scroll Title

anchor	Table_OBP_LED
title	On-board Push Buttons

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Designator	Connected to	Functionality	Note
S1	RESET	General reset
S2	USER_BTN	User push button	Connected to FPGA Bank 8.

Clock Sources

Scroll Title

anchor	Table_OBP_CLK
title	Osillators

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Clock Source

Schematic Name

Frequency

Note

Microchip MEMS Oscillator, U7

CLK12M

12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommendedThe module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

Scroll Title

anchor	Table_PWR_PC
title	Power Consumption

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sortDirection	ASC
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FPGA	Typical Current
Intel MAX 10 10M08 FPGA SoCFPGA	TBD*

* TBD - To Be Determined

...

Scroll Title

anchor	Figure_PWR_PD
title	Power Distribution

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draw.io Diagram

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the Green green LED (D1) will be on.

Power Rails

Voltage

Scroll Title

anchor	Table_PWR_PR
title	Module power rails.

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Power Rail Name	Connector

Designator

VCC / VCCIO Schematic Name

J2 Pin

Connector

J9 Pin

Direction

Notes

VIN

J2-13

VIN

-

5VInput

Input	5 V - Pin Header
3.3V

J2-12

-

3.3V

	Output
5V

5V

J2-14

-

Output

J9

USB_VBUS

5V

-

J9-1

Input

5 V - USB Connector

Input

Trenz Electronic Documentation

Versions Compared

Old Version 79

New Version Current

Key

Block Diagram

Main Components

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

Micro

-USB Connector

JTAG Interface

On-board Peripherals

SDRAM

FTDI FT2232H

SPI Flash Memory

SPI Flash

EEPROM

EEPROM

ADC

LEDs

Push Bottuns

Clock Sources

Power and Power-On Sequence

Power Supply

Power Consumption

Power-On Sequence

Power Rails

Bank Voltages

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions