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Template Revision 2.7 - on construction
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Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
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Table of contents
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Overview
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Notes :
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Example show, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze with Linux example.
Refer to http://trenz.org/te0841-info for the current online version of this manual and other available documentation.
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- Add basic key futures, which can be tested with the design
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Revision History
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Release Notes and Know Issues
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- new Assembly variants
- add Linux
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TE0841-test_board_noprebuilt-vivado_2017.4-build_11_20180621164459.zip
TE0841-test_board-vivado_2017.4-build_11_20180621164432.zip
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- REV02 Board parts
- new SI5338 configuration (default REV02)
- change xilisf_v5_9 for N25Q512A11G1240E support
- Some changes on block design
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- initial release
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anchor | Table_KI |
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title | Known Issues |
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Requirements
Software
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- needed
- Vivado is included into Vitis installation
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- needed
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- optional
Hardware
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Notes :
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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anchor | Table_HWM |
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title | Hardware Modules |
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Design supports following carriers:
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title | Hardware Carrier |
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Additional HW Requirements:
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title | Additional Hardware |
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Content
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Notes :
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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title | Design sources |
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Additional Sources
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title | Additional design sources |
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Prebuilt
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File
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File-Extension
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Description
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Notes :
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:Xilinx Development Tools
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0xA00000 (increase automatically generate Boot partition), increase image size to A:, see TE0841 Test Board#Config
- Use TE Template from /os/petalinux
- XSA is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
"prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\<DDR size>" of the selected device
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Depending of PC performance this can take several minutes. Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis - (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
- Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "\firmware\microblaze_0\"
- (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
- Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu_te0841.elf"
Launch
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
optional "TE::pr_program_flash -swapp hello_te0841" possible - Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
- Connect JTAG and power on PCB
- Open Vivado HW Manager
- Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"
- Note SREC Bootloader try to find application on flash, this will stop, if Flash is empty.
Usage
- Prepare HW like described on section 54395771
- Connect UART USB (most cases same as JTAG)
- Power on PCB
Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR - Open Serial Console (e.g. putty)
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Boot process takes a while, please wait.
Linux
Note: Linux boot process is slower on Microblaze.
- Open Serial Console (e.g. putty)
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
Vivado HW Manager:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals (fm_si...) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz - SI will be configured with MCS firmware, default all off on PCB REV01, PCB REV02 SI5338 will be preconfigured.
- LED control via VIO
- MGT CLK Freq can be changed over BUFG_GT control signals divider
- MCS Reset possible via VIO
- MIG Reset is possible over VIO
- MCS can be disabled over VIO (For PCB REV01 MCS is enabled, fpr PCB REV02 MCS is disabled by default VIO)
- Set radix from VIO signals (fm_si...) to unsigned integer.
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System Design - Vivado
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Block Design
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*Note: REV01 has SI5338 programming default enabled and REV02 default disabled. SI5338 of REV02 is preprogrammed |
Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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title | _i_fm.xdc |
linenumbers | true |
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zynqmp_pmufw
Xilinx default PMU firmware.
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General Example:
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Template location: ./sw_lib/sw_apps/
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2019.2 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash (some reinitialisation)
SREC SPI Bootloader
Modified Xilinx SREC Bootloader. Changes: Correct flash typ and SRec Start address, some additional console outputs, see source code
Changed xilisf_v5_9 to support N25Q512_1V8 for SREC (changes on xilisf.c and xilisf_intelstm.h)
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\sw_lib\sw_services\xilisf_v5_9
xilisf_v5_14
TE modified 2019.2 xilisf_v5_14
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Description currently not available.
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- (Set kernel flash Address to 0xA00000 and Kernel size to 0xA00000)
U-Boot
Start with petalinux-config -c u-boot
Changes:
- No changes.
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