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LabX Demo

This design converts TE0725 into mini lab instrument:

  • I/O Monitor and excerciser (all 84 I/O in B2B connectors)
  • 84 Channel Logic Analyzer, 4K deep (on A15T, an be larger with larger FPGA)
  • UART Echo with 1 Channel Logic Analyzer, 128K deep
  • 2 Channel Frequency Counter (each channel can use any pin from one connector)
  • 2 Channel Duty Cycle Instrument (each channel can use any pin from one connector)
  • POF Cable testing, Frequency, Duty and Logic Analyzer
ILA Core NameSample RateDepthConnection
xmod_uart10MHz10 MS/s128KUART RXD in XMOD connector
POF375MHz1 GS/s4K128KLVDS input from POF fibre receiver
J1_J2100MHz100 MS/s4KJ1: 42 pins, J2: 42 pins

Sample depths can be increased for all modules with FPGA's larger than A15T.

Channel NameMeasurement TypeConnection
CFCLKFrequencyFree running configuration clock, nominal 66MHz
J1_FREQFrequencyinput multiplexer, from any pin in J1
J1_DUTYDuty Cycleinput multiplexer, from any pin in J1
J2_FREQFrequencyinput multiplexer, from any pin in J2
J2_DUTYDuty Cycleinput multiplexer, from any pin in J2
POF_FREQFrequencyLVDS input from POF receiver
POF_DUTYDuty CycleLVDS input from POF receiver

...

Example screenshot, Uppercase "U" (HEX 0x55, binary 01010101) was sent from UART at 115200 baud, trigger on RXD 0 logic analyzer trace captured.logic level 0.

Image Added

125MHz signal sent to POF cable and received from the LVDS input, captured with 250MHz I/O sample clock, 4 samples per clock at data rate of 1GS/s.