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Table of Contents
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Overview
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Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0808" for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0808 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, max. 8 GByte up to 8 GBytes of DDR4 SDRAM with via 64-Bit width databus connectionbit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the most competitive price.
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Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
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Note |
Important Information for TE0808 boards which are equipped with ES1 or ES2 silicon: Erratas and functional restrictions may exist, please check Xilinx documentation and contact your local Xilinx FAE for restrictions. |
Key Features
- MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
- Memory
- 64-Bit DDR4, 8 GByte maximum
- Dual SPI boot Flash in parallel, 512 MByte maximum - User I/OOs
- 65 x MIOPS MIOs, 48 x PL HD (all)GPIOs, 156 x PL HP GPIOs (3 banks)
- Serial transceivertransceivers: 4 x GTR + 16 x GTH
- Transceiver clocks inputs and outputs
- PLL clock generator inputs and outputs - Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
- B2B connectors: 4 x 160 pin
- Si5345 - 10 output Si5345 - 10 output PLL
- All power supplies on board, single 3.3V power source required
- 14 on-board DCDC DC-DC regulators and 13 LDOs
- LP, FP, PL separately controlled power domains - Support for all boot modes (except NAND) and scenarios
- Support for any combination of PS connected peripherals
- Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
- B2B connectors: 4 x 160 pin
Block Diagram
Figure 1: TE0808-04 Block Diagram.
Main Components
Figure 2: TE0808 MPSoC module.
- Xilinx ZYNQ UltraScale+ XCZU9EG MPSoC, U1
- Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
- Red LED (DONE), D1
- 256Mx16 DDR4-2400 SDRAM, U12
- 256Mx16 DDR4-2400 SDRAM, U9
- 256Mx16 DDR4-2400 SDRAM, U2
- 256Mx16 DDR4-2400 SDRAM, U3
- 12A PowerSoC DCDC DC-DC converter, U4
- Quartz crystal, Y1
- Low-power programmable oscillator @ 25.000000 MHz (IN0 for U5), U25
- 10-channel programmable PLL clock generator, U5
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
- Quartz crystal, Y2
- 256 Mbit serial NOR Flash memory, U7
- 256 Mbit serial NOR Flash memory, U17
...
Table 1: Initial Delivery State of the flash memories.
Signals, Interfaces and Pins
...
Each connector has a specific arrangement of the signal pins, which are grouped together in categories related to their functionalities and to their belonging to particular units of the Zynq UltrascaleUltraScale+ MPSoC like I/O - banks, interfaces and Gigabit transceivers
or to the on-board peripherals.
...
Bank | Type | B2B Connector | Schematic Names / Connector Pins | I/O Signal CountSignals | LVDS Pairs Count | VCCO Bank Voltage | Notes | ||
---|---|---|---|---|---|---|---|---|---|
47 | HD | J3 | B47_L1_P ... B47_L12_P | 24 I/O'sOs | 12 | VCCO47 | VCCO max. 3.3V | ||
48 | HD | J3 | B48_L1_P ... B48_L12_P | 24 I/O'sOs | 12 | VCCO48 | VCCO max. 3.3V | ||
64 | HP | J4 | B64_L1_P ... B64_L24_P B_64_T0 ... B_64_T3 | 52 I/O48 I/O's | 24 | VCCO64 | VCCO max. 1.8V | ||
6465 | HP | J4 | B65_L1_P ... B65_L24_P B_6465_T0 ... B_6465_T3pins J4-8, J4-6, J4-4, J4-2 | 4 I/O's | - | 52 I/Os | 24 | VCCO65VCCO64 | VCCO max. 1.8V usable as single-ended I/ O'sOs |
6566 | HP | J4J1 | B65B66_L1_P ... B65B66_L24_P B_66_T0 ... B_66_T3 | 48 I/O'sOs | 24 | VCCO66VCCO65 | VCCO max. 1.8V | ||
65500 | HPMIO | J4 | J3 | MIO13 B_65_T0 ... B_65_T3 pins J4-7, J4-5, J4-3, J4-1 | 4 I/O's | - | VCCO65 | VCCO max. 1.8V only single-ended I/O's | |
66 | HP | J1 | B66_L1_P ... B66_L24_P | 48 I/O's | 24 | VCCO66 | VCCO max. 1.8V | ||
66 | HP | J1 | B_66_T0 ... B_66_T3 | 4 I/O's | - | VCCO66 | VCCO max. 1.8V | ||
500 | MIO | J3 | MIO13 ... MIO25 | 13 I/O's | - | PS_1V8 | user configurable I/O's on B2B | ||
501 | MIO | J3 | MIO26 ... MIO51 | 26 I/O's | - | PS_1V8 | user configurable I/O's on B2B | ||
502 | MIO | J3 | MIO52 ... MIO77 | 26 I/O's | - | PS_1V8 | user configurable I/O's on B2B |
Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-04 SoM
All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
For detailed information about the B2B pin-out, please refer to the Pin-out table.
The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.
MGT Lanes
The B2B connector J1 and J2 provide also access to the MGT-banks of the Zynq Ultrascale+ MPSoC. There are 20 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).
The MGT-banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT-lanes are available on the B2B connectors:
MIO25 | 13 I/Os | - | PS_1V8 | User configurable I/Os on B2B | |||
501 | MIO | J3 | MIO26 ... MIO51 | 26 I/Os | - | PS_1V8 | User configurable I/Os on B2B |
502 | MIO | J3 | MIO52 ... MIO77 | 26 I/Os | - | PS_1V8 | User configurable I/Os on B2B |
Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-04 SoM.
All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.
For detailed information about the B2B pin-out, please refer to the Pin-out table.
The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.
MGT Lanes
The B2B connector J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 20 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).
The MGT banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT lanes are available on the B2B connectors:
Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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228 | GTH | J1 | 4 GTH lanes (4 RX / 4 TX) | B228_RX3_P, B228_RX3_N, pins J1-51, J1-53 B228_RX2_P, B228_RX2_N, pins J1-57, J1-59 B228_RX1_P, B228_RX1_N, pins J1-63, J1-65 B228_RX0_P, B228_RX0_N, pins J1-69, J1-71 | 1 reference clock signal (B228_CLK0) from B2B connector 1 reference clock signal (B228_CLK1) from programmable | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
229 | GTH | J1 | 4 GTH lanes (4 RX / 4 TX) | B229_RX3_P, B229 | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
228 | GTH | J1 | 4 GTH lanes | B228_RX3_P, B228_RX3_N, pins J1-27, J1-29 B228B229_RX2_P, B228B229_RX2_N, pins J1-33, J1-35 B228B229_RX1_P, B228B229_RX1_N, pins J1-39, J1-41 B228B229_RX0_P, B228B229_RX0_N, pins J1-45, J1-47 | 1 reference clock signal (B228B229_CLK0) from B2B connector 1 reference clock signal (B228B229_CLK1) from programmable | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
229230 | GTH | J1 | 4 GTH lanes (4 RX / 4 TX) | B230B229_RX3_P, B229B230_RX3_N, pins J1-273, J1-295 B229B230_RX2_P, B229B230_RX2_N, pins J1-339, J1-3511 B229B230_RX1_P, B229B230_RX1_N, pins J1-3915, J1-4117 B229B230_RX0_P, B229B230_RX0_N, pins J1-4521, J1-4723 | 1 reference clock signal (B229B230_CLK0CLK1) from B2B connector 1 reference clock signal (B229B230_CLK1CLK0) from programmable | 230||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
128 | GTH | J1J2 | 4 GTH lanes | B230(4 RX / 4 TX) | B128_RX3_ | PN, | B230B128_RX3_ | NP, pins | J1J2- | 328, | J1J2- | 530 | B230B128_TX3_ | PN, | B230B128_TX3_ | NP, pins | J1J2- | 225, | J1J2- | 427 | B230B128_RX2_ | PN, | B230B128_RX2_ | NP, pins | J1J2- | 934, | J1J2- | 1136 | B230B128_TX2_ | PN, | B230B128_TX2_ | NP, pins | J1J2- | 831, | J1J2- | 1033 | B230B128_RX1_ | PN, | B230B128_RX1_ | NP, pins | J1J2- | 1540, | J1J2- | 1742 | B230B128_TX1_ | PN, | B230B128_TX1_ | NP, pins | J1J2- | 1437, | J1J2- | 1639 | B230B128_RX0_ | PN, | B230B128_RX0_ | NP, pins | J1J2- | 2146, | J1J2- | 2348 | B230B128_TX0_ | PN, | B230B128_TX0_ | NP, pins | J1J2- | 2043, | J1J2- | 2245 | 1 reference clock signal (B230B128_CLK1) from B2B connector 1 reference clock signal (B230B128_CLK0) from programmable |
128505 | GTHGTR | J2 | 4 GTHGTR lanes (4 RX / 4 TX) | B505B128_RX3_N, B128B505_RX3_P, pins J2-2852, J2-3054 B128B505_RX2_N, B128B505_RX2_P, pins J2-3458, J2-3660 B128B505_RX1_N, B128B505_RX1_P, pins J2-4064, J2-4266 B128B505_RX0_N, B128B505_RX0_P, pins J2-4670, J2-4872 | 1 2 reference clock signal (B128signals (B505_CLK0, B505_CLK1) from B2B connector 2 1 reference clock signal (B128_CLK0B505_CLK2, B505_CLK3) from programmable | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
505 | GTR | J2 | 4 GTR lanes | B505_RX3_N, B505_RX3_P, pins J2-52, J2-54 B505_RX2_N, B505_RX2_P, pins J2-58, J2-60 B505_RX1_N, B505_RX1_P, pins J2-64, J2-66 B505_RX0_N, B505_RX0_P, pins J2-70, J2-72 | 2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector 2 reference clock signal (B505_CLK2, B505_CLK3) from programmable |
Table 3: B2B connector pin-outs of available MGT-lanes of the MPSoC
JTAG Interface
JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage 'PS_1V8'.
...
K25/K26, H25/H26 |
Table 3: B2B connector pin-outs of available MGT lanes of the MPSoC.
JTAG Interface
JTAG access is provided through the MPSoC's PS configuration bank 503 with bank voltage PS_1V8.
JTAG Signal | B2B Connector Pin |
---|---|
TCK | J2-120 |
TDI | J2-122 |
TDO | J2-124 |
TMS | J2-126 |
Table 4: B2B connector pin-out of JTAG interface.
Configuration Bank Control Signals
The Xilinx Zynq UltraScale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B connector J2.
For further information about the particular control signals and how to use and evaluate them, refer to the Xilinx Zynq UltraScale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.
Signal | B2B Connector Pin | Function |
---|---|---|
DONE | J2-116 | PL configuration completed. |
PROG_B | J2-100 | PL configuration reset signal. |
INIT_B | J2-98 | PS is initialized after a power-on reset. |
SRST_B | J2-96 | System reset. |
MODE0 ... MODE3 | J2-109/J2-107/J2-105/J2-103 | 4-bit boot mode pins. For further information about the boot modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM section 'Boot and Configuration'. |
ERR_STATUS / ERR_OUT | J2-86 / J2-88 | ERR_OUT signal is asserted for accidental loss of power, an error, or an exception in the MPSoC's Platform Management Unit (PMU). ERR_STATUS indicates a secure lock-down state. |
PUDC_B | J2-127 | Pull-up during configuration (pulled-up to PL_1V8). |
Table 5: B2B connector pin-out of MPSoC's PS configuration bank.
Analog Input
The Xilinx Zynq UltraScale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2
Table 4: B2B connector pin-out of JTAG interface
Configuration Bank Control Signals
The Xilinx Zynq Ultrascale+ MPSoC's PS configuration bank 503 control signal pins are accessible through B2B-connector J2.
For further information about the particular control signals and how to use and evaluate them, refer to the Xilinx Zynq Ultrascale+ MPSoC TRM and UltraScale Architecture Configuration - User Guide.
Signal | B2B Connector Pin | Function | ||
---|---|---|---|---|
V_P, V_N | J2-113, | DONE | J2-116 | PL configuration completed |
PROG_B | J2-100 | PL configuration reset signal | ||
INIT_B | J2-98 | PS is initialized after a power-on reset | ||
SRST_B | J2-96 | System reset | ||
MODE0 ... MODE3 | J2-109/J2-107/J2-105/J2-103 | 4-bit boot mode pins For further information about the boot-modes refer to the Xilinx Zynq Ultrascale+ MPSoC TRM | ||
ERR_STATUS / ERR_OUT | J2-86 / J2-88 | ERR_OUT signal is asserted for accidental loss of ERR_STATUS indicates a secure lockdown state | ||
PUDC_B | J2-127 | Pull-up during configuration (pulled-up to 'PL_1V8') |
Table 5: B2B connector pin-out of MPSoC's PS configuration bank
Analog Input
The Xilinx Zynq Ultrascale+ MPSoC provides differential pairs for analog input values. The pins are exposed to B2B-connector J2.
...
Table 6: B2B connector pin-out of analog input pins
Quad SPI Interface
Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
...
Table 7: MIO-pin assignment of the Quad SPI Flash memory ICs
Boot Process
The boot source of the Zynq Ultrascale MPSoC can be selected via 4 dedicated pins, which generate a 4-bit code to select the boot mode. The pins are accessible on B2B connector J2:
...
Table 8: Boot mode pins on B2B connector J2
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115 | System Monitor | |
DX_P, DX_N | J2-119, J2-121 | Temperature-sensing diode pins |
Table 6: B2B connector pin-out of analog input pins
Quad SPI Interface
Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
MIO | Signal Name | U7 Pin | MIO | Signal Name | U17 Pin | |
---|---|---|---|---|---|---|
0 | SPI Flash CLK | B2 | 7 | SPI Flash CS | C2 | |
1 | SPI Flash IO1 | D2 | 8 | SPI Flash IO0 | D3 | |
2 | SPI Flash IO2 | C4 | 9 | SPI Flash IO1 | D2 | |
3 | SPI Flash IO3 | D4 | 10 | SPI Flash IO2 | C4 | |
4 | SPI Flash IO0 | D3 | 11 | SPI Flash IO3 | D4 | |
5 | SPI Flash CS | C2 | 12 | SPI Flash CLK | B2 |
Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.
Boot Process
The boot device and mode of the Zynq UltraScale+ MPSoC can be selected via 4 dedicated pins accessible on B2B connector J2:
Boot Mode Pin | B2B Pin |
---|---|
PS_MODE0 | J2-109 |
PS_MODE1 | J2-107 |
PS_MODE2 | J2-105 |
PS_MODE3 | J2-103 |
Table 8: Boot mode pins on B2B connector J2.
Following boot modes are possible on the TE0808 UltraScale+ module by generating the corresponding 4-bit code by the pins PS_MODE0 ... PS_MODE3 (little-endian alignment):
Boot Mode | Mode Pins [3:0] | MIO Location | Description |
---|---|---|---|
JTAG | 0x0 | JTAG | Dedicated PS interface. |
QSPI32 | 0x2 | MIO[12:0] | Configured on module with dual QSPI Flash Memory. 32-bit addressing. |
SD0 | 0x3 | MIO[25:13] | Supports SD 2.0. |
SD1 | 0x5 | MIO[51:38] | Supports SD 2.0. |
eMMC_18 | 0x6 | MIO[22:13] | Supports eMMC 4.5 at 1.8V. |
USB 0 | 0x7 | MIO[52:63] | Supports USB 2.0 and USB 3.0. |
PJTAG_0 | 0x8 | MIO[29:26] | PS JTAG connection 0 option. |
SD1-LS | 0xE | MIO[51:39] | Supports SD 3.0 with a required SD 3.0 compliant level shifter. |
Table 9: Selectable boot modes by dedicated boot mode pins.
For functional details see ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).
On-board Peripherals
Flash
The TE0808 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.
Name | IC | Designator | PS7 | MIO | Notes |
---|---|---|---|---|---|
SPI Flash | N25Q256A11E1240E | U7 | QSPI0 | MIO0 ... |
...
Configured on module with dual QSPI Flash Memory.
32-bit addressing.
Supports single and dual parallel
configurations.
Stack and dual stack is not
supported.
...
Supports SD 3.0 with a required
SD 3.0 compliant level shifter.
Table 9: Selectable boot modes by dedicated boot mode pins
For Functional details see ug1085 - Zynq ultrascale TRM (Boot Modes Section).
On-board Peripherals
Flash
The TE0808 SoM can be configured with max. 512 MByte Flash memory for configuration and operation.
Name | IC | Designator | PS7 | MIO | Notes |
---|---|---|---|---|---|
SPI Flash | N25Q256A11E1240E | U7 | QSPI0 | MIO0 ... MIO5 | dual parallel booting possible, 32 MByte memory per Flash IC at standard configuration |
SPI Flash | N25Q256A11E1240E | U17 | QSPI0 | MIO7 ... MIO12 | as above |
Table 10: Peripherals connected to the PS MIO - pins.
DDR4 SDRAM
The TE0808-04 SoM is equipped with with four DDR4-2400 SDRAM modules chip with up to 8 GByte memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR - controller (bank 504) with a 64-bit databus widthdata bus.
Refer to the Xilinx Zynq UltrascaleUltraScale+ data sheet DS925 to get information, if datasheet DS925 for more information on whether the specific package of the Zynq UltrascaleUltraScale+ MPSoC equipped on module supports the maximum data transmission rate of 2400 MByte/s.
Programmable PLL Clock Generator
...
Input | Connected to | Frequency | Notes |
---|---|---|---|
IN0 | On-board Oscillator (U25) | 25.000000 MHz | - |
IN1 | B2B Connector pins J2-34, J2-1 6 (differential pair) | User | AC decoupling required on base |
IN2 | B2B Connector pins J3-66, J3-68 (differential pair) | User | AC decoupling required on base |
IN3 | OUT9 | User | Loop-back from OUT9 |
Output | Connected to | Frequency | Notes |
OUT0 | B2B Connector pins J2-3, J2-1 (differential pair) | User | Default off |
OUT1 | B230 CLK0 | User | Default off |
OUT2 | B229 CLK1 | User | Default off |
OUT3 | B228 CLK1 | User | Default off |
OUT4 | B505 CLK2 | User | Default off |
OUT5 | B505 CLK3 | User | Default off |
OUT6 | B128 CLK0 | User | Default off |
OUT7 | B2B Connector pins J2-713, J2-9 15 (differential pair) | User | Default off |
OUT8 | B2B Connector pins J2-137, J2-15 9 (differential pair) | User | Default off |
OUT9 | IN3 (Loop-back) | User | Default off |
XA/XB | Quartz (Y1) | 50.000 MHz | - |
Table 11: Programmable PLL clock generator input/output.
The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.
Signal | B2B Connector Pin | Function |
---|---|---|
PLL_FINC | J2-81 | Frequency Incrementincrement. |
PLL_LOLN | J2-85 | Loss Of Lock of lock (active-low-active). |
PLL_SEL0 / PLL_SEL1 | J2-93 / J2-87 | Manual Input Switchinginput switching. |
PLL_FDEC | J2-94 | Frequency Decrementdecrement. |
PLL_RST | J2-5989 | Device Reset reset (active-low-active) |
PLL_SCL / PLL_SDA | J2-90 / J2-92 | I²C I2C interface, extern external pull-ups needed for SCL - / SDA -linelines. I²C I2C address in current configuration: 1101000b1101001b. |
Table 12: B2B connector pin-out of Si5345A programmable clock generator.
Note |
---|
Si5345 OTP ROM is not programmed by default at delivery, so it is customers responsibility to either configure Si5345 during FSBL or then use SiLabs programmer and burn program the OTP ROM with customer fixed clock setup. |
Si5345 OTP can only be programmed two times, as different user configurations may required different setup TE0808 is normally shipped with blank OTP.
For more information refer to Si5345 at SiLabs.
Oscillators
The TE0808-04 SoM is equipped with two on-board oscillators to provide the Zynq's MPSoC's PS configuration bank 503 with reference clock - signals.
Clock | Frequency | Bank 503 Pin | Connected to |
---|---|---|---|
PS_CLK | 33.333333 MHz | P20 | MEMS Oscillator, U32 |
PS_PAD (RTC) | 32.768 kHz | R22/R23 | Quartz crystal, Y2 |
Table 13: Reference clock-signals to PS configuration bank 503.
On-board LEDs
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | redRed | DONE signal (PS Configuration Bank 503) | This LED goes ON when power has been applied to the module and stays ON until MPSoC's programmable logic is configured properly. |
Table 14: LED's description.
Power and Power-On Sequence
...
The TE0808 module equipped with the Xilinx Zynq UltrascaleUltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltrascaleUltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular extern DCDC external DC-DC converters.
The Processing System contains three Power Domains:
...
On the TE0808-04 SoM, following Power Domains power domains can be powered up individually with power rails available on the B2B connectors:
- Full-Power Domainpower domain, supplied by power rail 'DCDCIN'
- Low-Power Domainpower domain, supplied by power rail 'LP_DCDC'
- Programmable Logiclogic, supplied by power rail' PL_DCIN'
- Battery Power Domainpower domain, supplied by power rail 'PS_BATT'
Each Power Domain power domain has its own "Enabling"- and "Power Good"-enable and power good signals. The power rail 'GT_DCDC' is necessary for generating is needed to generate the voltages for the Multi Gigabit Transceiver units of the Zynq UltrascaleUltraScale+ MPSoC.
Power Distribution Dependencies
The power rails ' DCDCIN', ' LP_DCDC', ' PL_DCIN', ' PS_BATT ' have to be powered up on the assigned pins of the B2B connectors as listed on the section "Power Rails". Except 'PS_BATT' (see section "Recommended Operation Conditions"), all power-rails can be powered up, with from 3.3V power sources , also shared(also share the same source, if Power Domain power domain control is not required).
There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DCDC DC-DC converters, which power up further DCDC DC-DC converters and the particular on-board voltages:
...
Figure 3: Power Distribution Diagram.
Note |
---|
Current rating of Samtec Razor Beam™ LSHMBeam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 21.0A 5 A per pin (2 adjacent pins powered1 pin powered per row). |
Power-On Sequence Diagram
The TE0808 SoM meets the recommended criteria to power up the Xilinx Zynq UltrascaleUltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DCDC DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
The on-board voltages of the TE0808 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DCDC converters. The on-board voltages will be powered up at three steps.
- Low-Power Domain (LPD) and on-board Si5345A programmable clock generator supply voltage
- Programmable Logic (PL) and Full-Power Domain (FPD)
- GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.
Following diagram clarifies the sequence of enabling the three power instances utilizing the DCDC converter control signals ('Enable', 'Power-Good'), which will power-up in descending order as listed in the blocks of the diagram.
Figure 4: Power-On Sequence Utilizing DCDC Converter Control Signals
Operation Conditions of the DCDC Converter Control Signals
The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good-Signals need extern pull-up resistors.
...
TPS82085SIL /
NC7S08P5X data sheet
...
up the on-board voltages.
The on-board voltages of the TE0808 SoM will be powered-up in order of a determined sequence by activating the above-mentioned power rails and the Enable-Signals of the DC-DC converters. The on-board voltages will be powered up at three steps.
- Low-Power Domain (LPD) and on-board Si5345A programmable clock generator supply voltage
- Programmable Logic (PL) and Full-Power Domain (FPD)
- GTH, PS GTR transceiver and DDR memory
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance has to be asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
Figure 4: Power-On Sequence Utilizing DC-DC Converter Control Signals.
Operation Conditions of the DC-DC Converter Control Signals
The control signals have to be asserted on the B2B connector J2, whereby some of the Power-Good signals need external pull-up resistors.
Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | |
---|---|---|---|---|---|---|---|---|
EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | |
EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | |
EN_PL | J2-101 | PL_DCIN | left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | 4K7, pulled up to PL_DCIN | TPS82085SIL / | |
EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | |
EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | |
EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74401 data sheet | |
EN_GT_L | J2-79 | GT_DCDC | NC7S08P5X data sheet | PG_GT_L | J2-97 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS74801 data sheet | |
EN_PLL_PWR | J2-77 | 6V | TPS82085SIL data sheet | PG_PLL_1V8 | J2-80 | External pull-up needed (max. 5.5V), max. sink current 1 mA | TPS82085SIL data sheet |
Table 16: Recommended operation conditions of DC-DC converter control signals.
Warning |
---|
To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/Os should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.
It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 SoM.
Voltage Monitor Circuit
The voltages LP_DCDC and LP_0V85 are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at power-on. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.
Figure 5: Voltage monitor circuit
Power Rails
Power Rail Name | B2B J1 Pins | B2B J2 Pins | B2B J3 Pins | Directions | Note |
---|---|---|---|---|---|
PL_DCIN | 151, 153, 155, 157, 159 | - | - | Input | - |
DCDCIN | - | 154, 156, 158, 160, | - | Input | - |
LP_DCDC | - | 138, 140, 142, 144 | - | Input | - |
PS_BATT | - | 125 | - | Input | - |
GT_DCDC | - | - | 157, 158, 159, 160 | Input | - |
PLL_3V3 | - | - | 152 | Input | U5 (programmable PLL) 3.3V nominal input |
SI_PLL_1V8 | - | - | 151 | Output | Internal voltage level 1.8V nominal output |
PS_1V8 | - | 99 | 147, 148 | Output | Internal voltage level |
PL_1V8 | 91, 121 | - | - | Output | Internal voltage level |
DDR_1V2 | - | 135 | - | Output | Internal voltage level |
Table 17: Power rails of the MPSoC module on accessible connectors.
Bank Voltages
Bank | Type | Schematic Name / B2B Connector Pins | Voltage | Reference Input Voltage | Voltage Range |
---|---|---|---|---|---|
47 | HD | VCCO47, pins J3-43, J3-44 | user | - | max. 3.3V |
48 | HD | VCCO48, pins J3-15, J3-16 | user | - | max. 3.3V |
64 | HP | VCCO64, J4-58, J4-106 | user | VREF_64, pin J4-88 | max. 1.8V |
65 | HP | VCCO65, J4-69, J4-105 | user | VREF_65, pin J4-15 | max. 1.8V |
66 | HP | VCCO66, J1-90, J1-120 | user | VREF_66, pin J1-108 | max. 1.8V |
500 | MIO | PS_1V8 | 1.8V | - | - |
501 | MIO | PS_1V8 | 1.8V | - | - |
502 | MIO | PS_1V8 | 1.8V | - | - |
503 | CONFIG | PS_1V8 | 1.8V | - | - |
Table 18: Range of MPSoC module's bank voltages.
B2B connectors
Include Page | ||||
---|---|---|---|---|
|
Variants Currently In Production
Module Variant | Zynq UltraScale+ MPSoC | DDR4 | Junction Temperature | Operating Temperature Range |
---|---|---|---|---|
TE0808-04-09EG-1EA | XCZU9EG-1FFVC900E | 2GB | 0°C - 100°C | Extended Temperature Range |
TE0808-04-09EG-1EB | XCZU9EG-1FFVC900E | 4GB | 0°C - 100°C | Extended Temperature Range |
TE0808-04-09EG-1ED(1) | XCZU9EG-1FFVC900E | 4GB | 0°C - 100°C | Extended Temperature Range |
TE0808-04-09EG-2IB | XCZU9EG-2FFVC900I | 4GB | -40°C - 100°C | Industrial Temperature Range |
(1) Note: Lower B2B connector profile,check distance bolt of between module and carrier
Table 19: Differences between variants of Module TE0808-04
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Unit | Notes / Reference Document |
---|---|---|---|---|
PL_DCIN | -0.3 | 4 | V | TPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG |
DCDCIN | -0.3 | 4 | V | TPS82085SIL / TPS51206 data sheet / Limit is LP_DCDC over EN/PG |
LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
GT_DCDC | -0.3 | 4 | V | TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG |
PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
PLL_3V3 | -0.5 | 3.8 | V | Si5345/44/42 data sheet |
VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
VREF | -0.5 | 2 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
Receiver (RXP/RXN) and transmitter | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, |
"Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD) | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
Table 16: Recommended operation conditions of DCDC converter control signals
Warning |
---|
To avoid any damages to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like bank's I/O voltages (VCCOx) can be powered up.
It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good"-signals are high, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0808 SoM.
Voltage Monitor Circuit
The voltages 'LP_DCDC' and 'LP_0V85' are monitored by a the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.
Figure 5: Voltage monitor circuit
Power Rails
...
Voltages on B2B
Connectors
...
Input/
Output
...
-
...
J2-154, J2-156, J2-158, J2-160,
J2-153, J2-155, J2-157, J2-159
...
Internal voltage level
1.8V nominal output
...
Internal voltage level
1.8V nominal output
...
Internal voltage level
1.2V nominal output
Table 17: Power rails of the MPSoC module on accessible connectors
Bank Voltages
...
Table 18: Range of MPSoC module's bank voltages
B2B connectors
...
Variants Currently In Production
...
Table 19: Differences between variants of Module TE0808-04
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Unit | Notes / Reference Document | ||||||
---|---|---|---|---|---|---|---|---|---|---|
PL_DCIN | -03.3 | 73.6 | V | EN63A0QI / TPS82085SIL | / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG | |||||
DCDCIN | -03.3 | 73.6 | V | TPS82085SIL / | TPS51206TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG | |||||
LP_DCDC | -03.3 | 43.6 | V | TPS3106K33DBVR data sheet | ||||||
GT_DCDC | -03.3 | 73.6 | V | TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG | ||||||
PS_BATT | 1.2 | 1-0.5 | 2 | V | Xilinx DS925 data sheet | |||||
PLL_3V3 | -03.514 | 3.847 | V | Si5345/44/42 data sheet 3.3V typical | ||||||
VCCO for HD I/O banks | -01.514 | 3.4 | V | Xilinx DS925 data sheet | ||||||
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet | VREF | -0.5 | 95 | 1.92 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks. | -0.552 | VCCO + 0.552 | V | Xilinx DS925 data sheet | ||||||
I/O input voltage for HP I/O banks | -0.552 | VCCO + 0.55 | V | Xilinx DS925 data sheet | PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.552 | V | Xilinx DS925 data sheet | |
PS I/O input voltage (MIO pins) | data sheet,Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.512 | VCCO_PSIO + 0.2 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally | |||||
Voltage on input pins of NC7S08P5X 2-Input AND Gate | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, | ||||||
Voltage on input pins (nMR) pin 'MR' of | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, | ||||||
"Enable"-signals on TPS82085SIL ('EN_PLL_PWR', 'EN_LPD') | -0.3 | 7 | V | TPS82085SIL data sheet | ||||||
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
Note |
---|
Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
...
NC7S08P5X data sheet,
see schematic for VCC
...
Voltage on input pin 'MR' of
TPS3106K33DBVR Voltage Monitor, U41
...
TPS3106 data sheet,
VDD = LP_DCDC
Monitor, U41 | 0 | VDD | V | TPS3106 data sheet, |
Note |
---|
Please check Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 5mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Revision History
Hardware Revision History
Date | Revision | Notes | Link to PCN | Documentation Link |
---|---|---|---|---|
- | 04 | First production silicon | - | TE0808-04 |
- | 03 | Second ES production release | - | TE0808-03 |
2016-03-09 | 02 | First ES production release | - | TE0808-02 |
- | 01 | Prototypes | - | - |
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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2022-09-13 | v.41 | Vadim Yunitski |
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2021-09-07 | V.39 | John Hartfiel |
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2021-05-17 | v.37 | John Hartfiel |
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2021-03-11 | v.35 | Antti Lukats |
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2019-01-27 | v.30 | Martin Rohrmüller |
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2018-11-20 | v.29 | John Hartfiel |
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2018-08-27 | v.27 | John Hartfiel |
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2028-06-28 | v.26 | John Hartfiel |
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2017-11-13 | v.24 | Ali Naseri |
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2017-11-13 | John Hartfiel |
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2017-10-20 | v.21 | Ali Naseri |
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2017-08-28 | v.15 | John Hartfiel |
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2017-08-28 | v.14 | Jan Kumann |
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2017-08-15 | v.12 | Vitali Tsiukala | Changed signals count in the B2B connectors table | ||||||||||||||||||||||||||
2017-08-15 | v.11 |
Note |
---|
Please check Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Extended grade: 0°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Revision History
Hardware Revision History
...
Notes
...
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description | |||
---|---|---|---|---|---|---|
Page info | modified-date | modified-date | dateFormat | yyyy-MM-ddJohn Hartfiel, Ali Naseri |
| |
2017-02-06 | V1v.1 | Jan Kumann | Initial document |
Disclaimer
Include Page | ||||
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