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The Trenz Electronic TEBA0714 is a carrier for Trenz Electronic module TE0714 which is an industrial - grade ... module ... based on Xilinx ...module integrated with Xilinx Artix 7.
Refer to http://trenz.org/teba0714-info for the current online version of this manual and other available documentation.
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Notes :- short description of the PCB
- Short Link of the wiki resources reference:
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Key Features
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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly optionsKey optionsKey Features' must be split into 6 main groups:- FPGA/Module
- Package:
- Speed:
- Temperature:
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- Module:
- Trenz TE0714 Modulsockel (2x Samtec 100 Pin LSHM-Serienstecker)Speed:
- Temperature:
- On Board:
- 2 x User LEDs (rot/grünRed, Green)
- 1 x PROG_ DONE LED (rotRed)
- Interface:
- 2 x Pin - Header 50 polig 50 Pol. (FPGA Bank Ein- und Ausgänge und Stromversorgung)
- 1 x Pin-Header für FPGA Bank Stromversorgung VCCIO34 (1.8 VOUT, 2.5V, 3.3 VOUT)
- I/Os and Power)
- 2x Samtec 100 Pin LSHM Series Connectors1 x Pin-Header für FPGA Bank Stromversorgungr V_CFG (1.8 VOUT, 2.5V, 3.3 VOUT)
- 1 x XMOD JTAG/UART Adapter (TE0790) Pin-Header
- 1 x Pin - Header 16 polig Pol. (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
- 1 x Pin - Header 10 polig (Ein-/ und AusgängePol. (FPGA Bank I/Os and Power)
- 1 x SFP-Anschluss+ Connectors
- Power:
- 1 x LDO Spannungsregler Regulator
- 3.3 V auf 2.5 V3V Nominal Power supply
- Dimension: 30 mm x 40
Block Diagram
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| title | TEBA0714 block diagram |
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Main Components
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Notes :- Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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| anchor | Figure_OV_MC |
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| title | TEBA0714 main components |
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| revision | 6 |
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| diagramName | TEBA0714_OV_MC |
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| simpleViewer | false |
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- 6-SMT pin header J26 for selecting PL-bank I/O voltage6-, J26
- SMT pin header, J27 for selecting XMOD/JTAG VCCIO
- Samtec Razor Beam™ LSHM-150 B2B connector, JM1
- Board to Board (B2B) Connector, JM1
- Board to Board (B2B) ConnectorrSamtec Razor Beam™ LSHM-150 B2B connector, JM2
- XMOD header, JX1
- Voltage Regulator, U1
- User Red LED, D2
- User Green LED, D1 (redRed)
- SFP+ Connector, J1
- User Red LED D3, indicating FPGA's 'Programming DONE'-signal, D3
- 50 - pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
- 16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
- 10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
- (Not assembled), J20
- 16 pin header (Not assembled), J3,
- 10-pin header (Not assembled), J4
- 50-pin header (Not assembled), J1750-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)
Initial Delivery State
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| Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
- VCCIO voltage selection jumpers are all set to 1.8 V.
- Pin headers (not soldered to the board, but included in the package as separate component)
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| orientation | portrait |
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| Storage device name | Content | Notes |
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| --- | --- | --- |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Signal | MODE Signal State | Boot Mode | Note |
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| BOOTMODE |
high or open| 0 | Slave SelectMAP |
| | 1 | Master SPI |
, x4 Modelow or groundSlave Selects MAP |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| Signal | B2B | Signal State | Note |
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| PROG_B | JM1-94 | Active Low | Clear FPGA configuration (falling edge) configuration and initiate a new configuration sequenz (next rising edge). |
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Signals, Interfaces and Pins
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Notes :- For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connector:
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| orientation | portrait |
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| sortDirection | ASC |
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| B2B Connector | Interface | Number of I/O | Notes |
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JM1
| User I/O | 52 Single ended, 27 Differential | - | | MGT lanes | 4 Differential, 2 lanes |
| | MGT reference clock input | 2 Single ended, 1 Differential |
| | JTAG | 4 Single ended |
| | SoM control signals | 2 Single ended | 'PROG_B', ' DONE' | | JM2 | User I/O | 36 Single ended or 18 differential | - | | SFP+ Interface control signals | 8 Single ended |
| | QSPI interface | 6 Single ended |
| | UART interface | 2 Single ended |
| | User LEDs | 2 Single ended | Red, Green | | SoM control signals | 1 Single ended | 'BOOTMODE' |
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...
TEBA0714 is equipped with four pin headers J17, J20, J3 and J4 which are not assembled on the board, in case of need customer can solder the pins and have access to the signals in the following tableJTAG access to the TExxxx SoM through B2B connector JMX.
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| anchor | Table_SIP_JTGPinHeader |
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| title | JTAG pins connectionGeneral I/O to Pin headers information |
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| sortDirection | ASC |
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JTAG Signal | B2B Connector |
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| TCK | JM1-90 |
| TDI | JM1-86 |
| TDO | JM1-88 |
| TMS | JM1-92 |
MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
| Pin Header | Interface | Number of I/O | Notes |
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J17
| User I/O | 36 Single ended, 18 Differential | Module FPGA Bank 14 | | SPI interface | 6 Single ended | - | | Power | 4 Single ended | 3.3V, V_CFG | | J20 | User I/O | 42 Single ended or 21 differential | Module FPGA Bank 34 | | Power | 4 Single ended | 3.3V, V_CFG | | User LEDs | 2 Single ended | Red, Green | | SoM control signals | 1 Single ended | 'BOOTMODE' | | J3 | JTAG | 4 Single ended |
| | UART | 2 Single ended | B14_L25, B14_L0 | | ADC | 2 Single ended |
| | Clock | 2 Single ended, 1 Differential |
| | Power | 4 Single ended | 3.3V, V_CFG | | Control Signals | 2 Single ended | BOOTMODE, PROG_B | | J4 | User I/O | 6 Single ended or 3 differential |
| | Power | 2 Single ended | 3.3V, 3.3V_OUT |
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JTAG Interface Base
JTAG access to the mounted SoM is provided through B2B connector JM1 and JM2 and is also routed to the XMOD JTAG/UART header JX1.
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes :
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| anchor | Table_SIP_OBPJTG |
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| title | On board peripheralsJTAG pins connection |
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| orientation | portrait |
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| sortDirection | ASC |
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| sortByColumn | 1 |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| XMOD Header Pin | Schematic | B2B Connector | Pin Header | Note |
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| A | B14_L25 | JM2-97 | J3-4 | UART Transfer | | B | B14_L0 | JM2-99 | J3-7 | UART Receive | | E | BOOTMODE | JM2-100 | J3-9 |
| | G | PROG_B | JM1-94 | J3-11 |
| | C | TCK | JM1-90 | J3-4 |
| | D | TDI | JM1-86 | J3-10 |
| | F | TDO | JM1-88 | J3-8 |
| | H | TMS | JM1-92 | J3-12 |
| | 3.3V | 3.3V | JM1-97,99 | J3,J4,J17,J20 | Nominal Input Voltage | | VIO | V_CFG | - | J17-45 | Configuration Voltage |
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The DIP-switch S2 on XMOD Adapter TE0790 must be set as the following table.
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| anchor | Table_OBPSIP_RTCXMODS2 |
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| title | I2C interface MIOs and JTAG pins connection |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| MIO Pin | Schematic | U? Pin | Notes| S2 | Status | Description | Notes |
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| 1 | ON | Update Mode JTAG access to SC CPLD only |
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| 2 | OFF | Must be in OFF state always |
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| 3 | OFF | 3.3V is input | supplied from pin headers externally |
| 4 | OFF | VIO is input | supplied from pin header externally |
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SFP+ Connector
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| anchor | Table_OBP_I2C_RTCSIP_SFP+ |
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| title | I2C Address for RTCSFP+ Connector Information |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| MIO Pin | I2C Address | Designator | Notes |
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...
| Pin | Connected to | Notes |
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| VCCR | 3.3V |
| | VCCT | 3.3V |
| | VREF | GND |
| | TD+/TD- | MGT TX | MGT Lane | | RD+/RD- | MGT RX | MGT Lane | | TX/FAULT | SFP0_TX_FAUL | SFP_CTRL | | TX/DISABLE | SFP0_TX_DIS | SFP_CTRL | | MOD-DEF2 | SFP0_SDA | SFP_CTRL | | MOD-DEF1 | SFP0_SCL | SFP_CTRL | | MOD-DEF0 | SFP0_MT_DEF0 | SFP_CTRL | | RS0/RS1 | SFP0_RS0_1 | SFP_CTRL | | LOS | SFP0_LOS | SFP_CTRL |
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There are two SMT Pin Headers, J26-J27.
J26 is available to choose voltage level for VCCIO34 (FPGA Bank 34) and J27 is provided to set the voltage level of V_CFG (Configuration Voltage). In order to set the voltage level, you should connect it to the corresponding pin with the target value voltage.
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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| anchor | Table_OBPSIP_I2C_EEPROMSMD |
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| title | I2C address for EEPROMSMD Connector Information |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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MIO | I2C Address | Designator| VCCIO/VCC | Voltage Level | Notes |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
VCCIO34
| 1.8V |
| | 2.5V |
| | 3.3V | 3.3V_OUT | | J27 | V_CFG
| 1.8V |
| | 2.5V | V_CFG0 | | 3.3V | 3.3V_OUT |
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On-board Peripherals
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Notes :- add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Notes :In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connectionsOn board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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...
| Chip/Interface | Designator | Notes |
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| LEDs | D1...3 |
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LEDs
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| anchor | Table_OBP_CLKLED |
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| title | OsillatorsOn-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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DescriptionFrequency| MHz | | D1 | Green | GLED | Active High |
| | D2 | Red | RLED | Active High |
| | D3 | Red | DONE | Active Low | DONE pin |
MHz | KHz
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:- Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended3A for system startup is recommended.
The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.
Power Consumption
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
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| VIN3.3V | * TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Determined
Power Distribution Dependencies
3.3V can be supplied through Pin Headers on specific pins.
| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 9 |
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| diagramName | TEBA0714 |
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| Scroll Title |
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| anchor | Figure |
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| title | Power Distribution |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 640 |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power-On Sequence
There is no specific power-on sequence. After power on, the module and carrier will be powered on.
| Scroll Title |
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| anchor | Figure_PWR_PS |
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| title | Power Sequency |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Voltage Monitor Circuit
| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 3 |
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| diagramName | TEBA0714_PWR_PS |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 640 |
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| Scroll Title |
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| anchor | Figure_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
| | sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B , JM1 Pin | B2B JM2 Pin | Pin Header J17 | Pin Header J20 | Pin Header J3 | Pin Header J4 | Direction | Notes |
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| 3.3V | 99,97 | - | 5, 46 | 5, 46 | 5 | 5 | Input |
| | 1.8V | - | 18 | - | - | - | - | Input | Comes from Module | | 3.3V_OUT | 83 | 54 | - | - | - | 6 | Output |
| | VCCIO34 | 61 | - | - | 45 | - | - | Output | Variable voltage level | | V_CFG | 53 | - | - | - | - | - | Input | Variable voltage level |
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| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Board to Board Connectors
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- This section is optional and only for modules.
- use "include page" macro and link to the general B2B connector page of the module series,For example: 6 x 6 SoM LSHM B2B Connectors
PD: | 6 x 6 SoM LSHM B2B Connectors |
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PD: | 6 x 6 SoM LSHM B2B Connectors |
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? x ? modules use two or three Samtec Micro Tiger Eye ConnectorTEBA0714 carrier use two Samtec Razor Beam LSHM Connectors on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
| Include Page |
|---|
| 4 x 5 SoM LSHM B2B Connectors |
|---|
| 4 x 5 SoM LSHM B2B Connectors |
|---|
|
...
Technical Specifications
Absolute Maximum Ratings
| Scroll Title |
|---|
| anchor | Table_TS_AMR |
|---|
| title | PS absolute maximum ratings |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Symbols | Description | Min | Max | Unit |
|---|
|
|---|
| VIN | Input Supply Voltage | -0.3 | 6 |
V | VV | | T_STR | Storage Temperature | -40 | 125 | °C |
V | V | V | V
|
Recommended Operating Conditions
...
| Scroll Title |
|---|
| anchor | Table_TS_ROC |
|---|
| title | Recommended operating conditions. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting |
|---|
|
| true |
| Parameter | Min | Max | Units | Reference Document |
|---|
V | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | | Parameter | Min | Max | Units | Reference Document |
|---|
| VIN | 3.135 | 3.465 | V | 3.3V Nominal Power Supply |
| T_OPR | -40 | 85 | °C |
|
Physical Dimensions
- Module size: ?? 46 mm × ?? 75 mm. Please download the assembly diagram for exact numbers.
- Mating height with standard connectors: ? 8 mm.
PCB thickness: ?? 1.64 mm.
| Page properties |
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|
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
|
| Scroll Title |
|---|
| anchor | Figure_TS_PD |
|---|
| title | Physical Dimension |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 1 |
|---|
| diagramName | TEBA0714 |
|---|
|
|
|
| Scroll Title |
|---|
| anchor | Figure |
|---|
| title | Physical Dimension |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| diagramWidth | 641 |
|---|
|
| | Scroll Ignore |
|---|
| Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
|---|
| scroll-eclipsehelp | true |
|---|
| scroll-epub | true |
|---|
| scroll-html | true |
|---|
| true | | scroll-html | true |
|---|
|  Image Addedimage link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Currently Offered Variants
| Scroll Title |
|---|
| anchor | Table_VCP_SO |
|---|
| title | Trenz Electronic Shop Overview |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
Revision History
Hardware Revision History
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
|---|
| title | Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Changes | Documentation Link |
|---|
| 2016-06-15 | 01 | | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.dash.
| Scroll Title |
|---|
| anchor | Figure_RV_HRN |
|---|
| title | Board hardware revision number. |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName |
|---|
|
|
|
| Scroll Title |
|---|
anchor |
| title | Board hardware revision number. |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| diagramWidth | 146 |
|---|
| revision | 1 |
|---|
|
| | Scroll Ignore |
|---|
| Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed Image Added |
|
Document Change History
| Page properties |
|---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports
|
...
| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
|---|
| type | Flat |
|---|
|
| | Page info |
|---|
| infoType | Current version |
|---|
| prefix | v. |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| | Page info |
|---|
| infoType | Modified by |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| - change listInitial Release
| | -- | all | | Page info |
|---|
| infoType | Modified users |
|---|
| type | Flat |
|---|
| showVersions | false |
|---|
|
| |
|
Disclaimer
| Include Page |
|---|
| IN:Legal Notices |
|---|
| IN:Legal Notices |
|---|
|
...