Page History

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• Xilinx Zynq-7000 XC7Z045-2FFG900I SoC
• Rugged for shock and high vibration
• Large number of configurable I/Os are provided via rugged high-speed stacking strips
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32bit wide DDR3) connected to PS
  • 2 GByte RAM (64bit wide DDR3) connected to PL
  • 32 MByte QSPI Flash memory
  • Hi-Speed USB2 ULPI transceiver PHY
  • Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64 GByte)
• Lattice MachXO2 HC 4000 System Controller CPLD
  • 40 GPIO's available to user on B2B connector
• MAC-address EEPROM
• Serial user EEPROM
• Temperature compensated RTC (real-time clock)
• Si5338A programmable quad PLL clock generator for GTX transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • 4x GT transceiver clock inputs
  • 254 166 FPGA I/O's (125 83 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED

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The TE0783 boot mode is selected by the pin 'CPLD_GPIO3' of the SC CPLD, which is connected to B2B pin J2-16 to either boot from the on-board QSPI Flash memory U38 or SD IO interface. See section Bootmode in the TE0783 SC CPLD reference Wiki page.

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Special purpose pins are connected to System Controller CPLD (U32) and have following default configuration:

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GbE PHY connection:

Table 9: General overview of the Gigabit Ethernet1 PHY signals

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USB2 PHY connection:

Table 10: General overview of the Gigabit Ethernet2 PHY signals

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eMMC Flash memory device (U28) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

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DDR3L Memory

By default TE0783-01 module has two 16-bit 16bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) connected to the PS DDR memory bank 502, the chips are arranged into 32-bit 32bit wide memory bus providing total of 1 GBytes of on-board RAM.

Another 4 chips are arranged into 64bit wide memory bus prodivding total of 2 GByte on-board RAM connected to the PL HP banks 34, 35 and 36.

Quad SPI Flash MemoryQuad SPI Flash Memory

One quad SPI compatible serial bus Flash memory (U38) for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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Table 1412: General overview of the on-board quad clock generator I/O signals

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Table 1513: Reference clock signals

On-board LEDs

Table 1614: On-board LEDs

Power and Power-on Sequence

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Power supply with minimum current capability of 3A 4A for system startup is recommended.

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Table 1715: Power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

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The Trenz TE0783 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 3.3V_SB, 1.5V, VTT, VTTREF for PS and PL memory bank, 1.8V_MGT and VCCAUX_IO.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to

Power-On Sequence

The TE0820 SoM meets the recommended criteria to power up the Xilinx Zynq chip properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.Following diagram clarifies the sequence of enabling the , which power up further DC-DC converters and the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

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It is important that all carrier board I/Os are 3-stated at power-on until System Controller CPLD sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

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See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0783 module.

Power-On Sequence

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Voltage Monitor Circuit

The voltages '1V' and '3.3V' are monitored by the voltage monitor circuit U27, which generates the PS_POR reset signal if monitored voltages have transient interruptions:

Power Rails

Table 1816: Module power rails

Bank Voltages

Table 17Table 19: Module I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

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Board to Board Connectors

Variants Currently In Production

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Table 2018: Module absolute maximum ratings

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Table 2119: Recommended operating conditions

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Table 2220: Hardware revision history table

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Table 21Table 23: Document change history

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