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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

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• Xilinx
XA7Z020
• XC7Z020-1CLG484Q (Automotive)
• Rugged for shock and high vibration
• Dimensions: 6 x 6 cm
Temperature range: Automotive
• [XA7Z014S is available on other assembly options]
  • Package: CL/CLG484
  • Speed Grade: -1
  • Temperature Grade: Expanded (-40 to +128 °C)
• • 
    
• Dual-Core ARM Cortex-A9 MPCore
  
• 2 x 100 MBit Ethernet transceiver (PHY)
• 512 MByte DDR3L SDRAM, 16-bit-wide 
• DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
16 MByte
• QSPI Flash memory (with XiP support)
• [different size is available on other assembly options]
• Programmable SIT8918A , PS clock generator
• 2 Kbit serial EEPROM
• Three user LEDs
• CAN transceiver (PHY)
• Temperature compensated RTC (real-time clock)
• 2 x 100 MBit Ethernet transceiver (PHY)
• Board to Board (B2B)
  • Plug-on module
Plug-on module
• • with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
76 single ended
• I/O
, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectorsCAN transceiver (PHY)
• Interface
  • 42x MIO
  • 200x HR
  • 128x PS IO
  • 0x GTP Transceiver
  • 0x GTX Transceiver

• Power Supply
  • 12 V power supply with watchdog
• Others:
  • Dimensions: 6 x 6 cm
  • Rugged for shock and high vibration
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
Three user LEDs
• • Evenly-spread supply pins for good signal integrity
    
Other assembly options for cost or performance optimization plus high volume prices available on request.

Depending on the customer design, additional cooling might be required.

Block Diagram

Block Diagram

Main Components

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1. DDR3 SDRAM512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
3. 100 MBit Ethernet transceiver  DP83848transceiver, U3
4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
7. Real Time Clock, Micro Crystal RV-3029-C3, U7
8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
11. 64 Kbit I2C EEPROM, 24LC64, U11
12. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16

Initial Delivery State

1. 100 MBit Ethernet transceiver, U10
2. User LED Green, D4
3. Real Time Clock, U7
4. Standard Clock Oscillators, U5
5. 64 Kbit I2C EEPROM, U11
6. CAN Tranceiver, U16
7. QSPI NOR Flash memory, U13
8. Standard Clock Oscillators, U14
9. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
10. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
11. B2B connector , JM2
12. B2B connector , JM3
13. B2B connector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Configuration Signals

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

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B2B Pin

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There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

On-board Peripherals

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16 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided here. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

RTC I^₂C

The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.

EEPROM

The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

LEDs

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512 Mbyte DDR3L SDRAM

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

• Part number: NT5CC256M16DP Nanya
• Supply voltage: 1.35V
• Speed: 1600 Mbps
• NOR Flash
• Temperature: 0C~95C

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848-EP provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

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Signals, Interfaces and Pins

Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

CAN PHY

CAN pins connections to Board to Board (B2B).

JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

MIO Pins

On-board Peripherals

Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

RTC 

The RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC interrupt is connected to MIO0 connected to Bank 500 through pin G6.

EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

LEDs

DDR3 SDRAM

The TE0728 SoM has a volatile DDR3 SDRAM, 256Mx16bit (512MB), IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions.

• Part number: NT5CB256M16CP-DIH
• Supply voltage: 1.5V
• Organization: 256M x 16 bits

DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

Oscillators

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power on Sequence

The TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

It is recommended to add IOB TRUE constraint for the MII Interface pins.

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

CAN Transceiver

The SN65HVD230Q,  controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40C~125C.

Low Quiescent Current Programmable Delay Supervisory Circuit

The TPS3808G01-Q1 microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the useradjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

The TPS3808G01-Q1 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be useradjusted from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. The TPS3808G01-Q1 has a very low typical quiescent current of 2.4 μA, so it is well suited for battery-powered applications. 

Low Dropout Linear Regulator

The TPS74801-Q1 low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package.

Clock Sources

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Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

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* TBD - To Be Determined

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Power-On Sequence

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Power Rails

Bank Voltages

The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit

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B2B Connector

JM1 Pin

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B2B Connector

JM2 Pin

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B2B Connector

JM3 Pin

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1.8V

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Bank Voltages

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Bank          

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Voltage

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Board to Board Connectors

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Processing System(PS)

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Technical Specifications

Absolute Maximum Ratings

Programmable Logic(PL)

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Recommended Operating Conditionse

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Parameter

Symbol	Min	Max	Units	Reference Document

Recommended Operating Conditions

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Physical Dimensions

• Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 7 mm.

• PCB thickness: 1.6 mm.

Currently Offered Variants 

Physical Dimensions

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Revision History

Hardware Revision History

Product changes can be seen in PCN page.

Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

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