Page History

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On-board Peripheral	B2B	MPSoC Unit / SoM peripheral	Description	TRM Section
FMC HPC J5, 24 LVDS pairs (48 I/O's)	J1	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs	FMC HPC Connector
FMC HPC J5, GTH Interface	J1	MGT Bank	10 MGT Lanes	FMC HPC Connector
SFP+ 2x1 Cage J14	J1	MGT Bank	2 MGT Lanes to dual SFP+ Connector	MGT Interfaces SFP+ and FireFly
SMA Coax J33	J1	On-module PLL	SMA Coaxial Connector to on-module PLL Clock Input pin	Programmable PLL Clock Generator
FMC HPC J5 10 LVDS pairs (20 I/O's) 1 LVDS Clock to PL Bank 2 MGT Clocks to MGT Banks	J2	PL Bank (FMC_VADJ) MGT Bank	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair 2 MGT clock input pin-pairs	FMC HPC Connector Programmable PLL Clock Generator
24-bit Audio Codec U3	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board 24-bit Audio Codec	Intel-PC Compatible Headers and FAN Connectors 24-bit Audio Codec
10 I/O's to SC CPLD U17	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U17	System Controller CPDLsCPLDs
8 I/O's to SC CPLD U39	J3	PL Bank (1.8 V)	PL I/O-bank pins to on-board System Controller CPLD U39	System Controller CPDLsCPLDs
SDIO Interface, SD- / MMC-Card Mux	J3	PS MIO	SDIO interface connected to SD- / MMC-Card socket	MIO Bank Interfaces SDIO Port Expander
Board Peripheral's I²C Interfaces muxed to MPSoC I²C	J3	PS MIO	MPSoC I²C interface configured as master connected to on-board slaves	MIO Bank Interfaces 8-Channel I²C Switches
4 MIO to SC CPLD U17	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLsCPLDs
15 MIO to SC CPLD U39	J3	PS MIO	Functionality depending on MPSoC and CPLD firmware	System Controller CPDLs
Ethernet PHY RGMII	J3	PS MIO	Ethernet PHY U12 connected per RGMII	MIO Bank Interfaces Gigabit Ethernet PHY
eMMC Flash	J3	PS MIO	eMMC Flash memory interface on PS bank	MIO Bank Interfaces eMMC Memory
USB2.0 PHY ULPI	J2	PS MIO	USB2.0 PHY U9 connected per ULPI	MIO Bank Interfaces High-speed USB ULPI PHY
SAMTEC FireFly Connector J6/J15	J2	MGT Bank	MGT Lanes to Samtec FireFly connector	MGT Interfaces SFP+ and FireFly
JTAG Interface via XMOD Header J12	J2	PS Config	MPSoC USB programmable JTAG interface	MIO Bank Interfaces JTAG Interface
USB3.0 Lane	J2	PSGT	USB3.0 PS MGT Lane	MIO Bank Interfaces PS GT Bank Interfaces
4-port USB3.0 Hub	-	-	USB3.0 (2.0 compatible) Hub with 4 ports	MIO Bank Interfaces 4-port USB3.0 Hub
USB3.0 / RJ45 GbE Connector J7, USB3.0 Connector J8	-	-	2-port USB3.0 / RJ45 GbE Connector (stacked)	MIO Bank Interfaces
25 SoM Control Signals to SC CPLDs U17 / U39	J2	On-module DC-DC converter, PLL clock generator	Control Signals, e.g. "Enable"- / "Power Good"- signals of DC-DC-converter and further on-module peripherals	Power-On Sequence Diagram Programmable PLL Clock Generator
150 MHz Osci Clock Input	J2	-	150 MHz SATA interface MGT clock	Oscillators
Signals DONE, INIT_B, SRST_B, ... to SC CPLD U39	J2	PS Config	MPSoC control signal for PS- / PL configuration	System Controller CPDLsCPLDs
SATA Connector J31 PCIe Connector J1 DisplayPort J13	J2	PSGT	Connectors of the MGT based data interfaces	PS GT Bank Interfaces
PLL Clock Output to PCIe Interface On-board PLL U35 MGT Bank (B2B J3)	J2	On-module PLL clock generator	Reference clock signals of the on-module programmable PLL clock generator	Programmable PLL Clock Generator
4 I/O's to PMOD P2 via IC U33	J4	PL Bank (FMC_VADJ)	PL user I/O's accessible on PMOD connector P2	CAN FD Interface and PMOD Connectors
3 I/O's to SC CPLD U17 via IC U32	J4	PL Bank (FMC_VADJ)	PL user I/O's routed to System Controller CPLD U17	System Controller CPDLsCPLDs
FMC HPC J5 46 LVDS pairs (92 I/O's) 1 LVDS Clock to PL Bank	J4	PL Bank (FMC_VADJ)	PL I/O-bank pins, differential pairs 1 clock capable PL bank pin-pair	FMC HPC Connector Programmable PLL Clock Generator

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The System Controller CPLDs will be programmed by the XMOD-Header J28 in a cascaded JTAG chain as visualized in Figure 89. To program the System Controller CPLDs, the JTAG interface of these devices have to be activated by DIP-switch S4-3.
The 4 GPIO/UART pins (XMOD1_A/B/E/G) of the XMOD-Header J28 are routed to the System Controller CPLD U17.

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Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U10	USB0_RCLK	52.000000 MHz	USB 2.0 transceiver PHY U9, pin 26
SiTime SiT8008BI oscillator, U13	ETH_CLK	25.000000 MHz	Gigabit Ethernet PHY U12, pin 34
SiTime SiT8008BI oscillator, U7	-	25.000000 MHz	Quad PLL clock generator U35, pin 3
DSC1123 oscillator, U23	B505_CLK1	150.0000 MHz	PS GT Bank, dedicated for SATA interface
DSC1123 oscillator, U6 optional, not equipped	B505_CLK0	100.0000 MHz	PS GT Bank, dedicated for USB interface
Silicon Labs 570FBB000290DG, U45 optional, not equipped	B47_L5 (LVDS)	250.MHz	PL Bank clock capable input pins
SiTime SiT8008BI oscillator, U25	CLK_CPLD	2524.576000 MHz	System Controller CPLD U35, pin 128

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I²C Slave Devices connected to MPSoC I²C Interface	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
8-channel I²C switch U16	-	0x73	I2C_SDA / I2C_SCL
8-channel I²C switch U27	-	0x77	I2C_SDA / I2C_SCL
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL)	-	User programmable	I2C_SDA / I2C_SCL
I²C Slave Devices connected to 8-channel I²C Switch U16	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
On-board Quad programmable PLL clock generator U35 Si5338	0	0x70	MCLK_SDA / MCLK_SCL
8-bit I²C IO Expander U44	1	0x26	SFP_SDA / SFP_SCL
PCIe Connector J1	2	module dependent	PCIE_SDA / PCIE_SCL
SFP+ Connector J14A	3	module dependent	SFP1_SDA / SFP1_SCL
SFP+ Connector J14B	4	module dependent	SFP2_SDA / SFP2_SCL
Configuration EEPROM U24U42	5	0x54	MEM_SDA / MEM_SCL
Configuration EEPROM U36	5	0x52	MEM_SDA / MEM_SCL
Configuration EEPROM U41	5	0x51	MEM_SDA / MEM_SCL
Configuration EEPROM U22	5	0x50	MEM_SDA / MEM_SCL
8-bit I²C IO Expander U38	5	0x27	MEM_SDA / MEM_SCL
FMC Connector J5	6	module dependent	FMC_SDA / FMC_SCL
USB3.0 Hub configuration EEPROM U5	7	0x51	USBH_SDA / USBH_SCL
USB3.0 Hub	7	0x60	USBH_SDA / USBH_SCL
I²C Slave Devices connected to 8-channel I²C Switch U27	I²C Switch Position	I²C Slave Address	Schematic Names of I²C Bus Lines
PMOD Connector P1	0	module dependent	PMOD_SDA / PMOD_SCL
24-bit Audio Codec U3	1	0x38	A_I2C_SDA / A_I2C_SCL
FireFly Connector J15	2	module dependent	FFA_SDA / FFA_SCL
FireFly Connector J22	3	module dependent	FFB_SDA / FFB_SCL
On-module Quad programmable PLL clock generator Si5345 (TE0808)	4	0x69	PLL_SDA / PLL_SCL
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL)	5	User programmable	SC_SDA / SC_SCL
8-bit I²C IO Expander U34	6	0x24	FF_E_SDA / FF_E_SCL
PMOD Connector P3	7	module dependent	EXT_SDA / EXT_SCL

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EEPROM Modell	Schematic Designator	Memory Density	Purpose
24LC128-I/ST	U24U30	128 Kbit	user
24AA025E48T-I/OT	U36	2 Kbit	user
24AA025E48T-I/OT	U41	2 Kbit	user
24AA025E48T-I/OT	U42	2 Kbit	user
24LC128-I/ST	U5	128 Kbit	USB3.0 Hub U4 configuration memory

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Figure 13: Power-On Sequence Utilizing DCDC Converter Control Signals

Note

As shown in Figure 1213, the DIP switch S4-4 has to be closed if using only 12V single power supply through 12V power jack J25, otherwise the 5V voltage level will not be enabled to generate the 3V3SB voltage to power up the SC CPLD U39 and starting the power-on sequence.
By using an ATX-24 power connector on J20, there is usually also a 5V supply voltage provided, hence the DIP switch S4-4 is not relevant in this case of power supply.

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
dateFormat	yyyy-MM-dd
prefix	v.
type	Flat

Page info

infoType	Modified by
dateFormat	yyyy-MM-dd
type	Flat

update System Controller links fixed

2019-09-03

v.96

Thomas Steffens

correction EEPROM Designator
correction typ U25 CLK

2018-07-02

02 Jul 2018

v.89

Martin Rohrmüller

Typo

2018-05-31

May 2018

v.88

John Hartfiel

Typo correction Table 13
Typo correction Table 9

2017-11-15

v.86

Ali Naseri

DIP-switches section revised and updated

2017-11-13

v.82

Ali Naseri

updated B2B connector max. current rating
per pin

2017-11-13

v.80

John Hartfiel

rework B2B section

2017-10-19

v.79

Ali Naseri

added additionally MGT lanes information

2017-10-18

v.75

Ali Naseri

added Power Rails section

2017-08-29

v.70

John Hartfiel

update document change history
published

2017-08-28

v.69

Ali Naseri

Initial document

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all

Page info

infoType	Modified users
type	Flat
showVersions	false

--

Table 36: Document change history.

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Trenz Electronic Documentation

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