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Refer to http://trenz.org/te0xyzte0803-info for the current online version of this manual and other available documentation.

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Excerpt
  • Vitis/Vivado 2019.2
  • PetaLinux
  • Linux Debian 9 (Stretch) or Linux Ubuntu 18.04 (Bionic Beaver)
  • DisplayPort
  • SD
  • ETH (use EEPROM MAC)
  • MAC from EEPROM
  • PCIe
  • USB
  • I2C
  • TEBF0808

  • RTCRGPIO
  • SATAFMeter
  • user LED access
  • Modified FSBL for SI5338 programming
  • Special FSBL for QSPI programming

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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2020-05-
04
082019.2
TE0820

TE0803-

test

SK_DEMO1_

board

noprebuilt-vivado_2019.2-build_

3

11_

20200114081551

20200508143345.zip

TE0820

TE0803-

test

SK_

board_noprebuilt

DEMO1-vivado_2019.2-build_

3

11_

20200114081612

20200508143327.zip

Mohsen Chamanbaz
  • initial release


Release Notes and Know Issues

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titleSoftware

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SoftwareVersionNote
Vitis2019.2needed, Vivado is included into Vitis installation
PetaLinux2019.2needed

SD Card Formatter


format SD Card

Win32 DiskImager


burn generated image on SD
SI ClockBuilder Pro----optional


Hardware

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Notes :

  • list of software which was used to generate the design

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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes

Design supports following carriers:

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titleHardware Carrier

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Additional HW Requirements:

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titleAdditional Hardware

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Content

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Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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titleDesign sources

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TE0803-ES1         es1_2gb    REV01      2GB      64MB       NA         NA               Not longer supported by vivado   
TE0803-01-02EG-1E  2eg_2gb    REV01      2GB      64MB       NA         NA               NA                                 
TE0803-01-02CG-1E  2cg_2gb    REV01      2GB      64MB       NA         NA               NA                                 
TE0803-01-03EG-1E  3eg_2gb    REV01      2GB      64MB       NA         NA               NA                                 
TE0803-01-03CG-1E  3cg_2gb    REV01      2GB      64MB       NA         NA               NA                                 
TE0803-01-02EG-1EA 2eg_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-02CG-1EA 2cg_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-03EG-1EA 3eg_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-03CG-1EA 3cg_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-02-03EG-1EB 3eg_4gb    REV02|REV014GB      128MB      NA         NA               NA                                 
TE0803-01-04CG-1EA 4cg_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-04EV-1EA 4ev_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-04EV-1E3 4ev_2gb    REV01      2GB      128MB      NA         1 mm connectorsNA                                 
TE0803-01-04EG-1EA 4eg_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-04CG-1EB 4cg_2gb    REV01      2GB      256MB      NA         NA               NA                                 
TE0803-01-05EV-1EA 5ev_2gb    REV01      2GB      128MB      NA         NA               NA                                 
TE0803-01-05EV-1IA 5ev_i_2gb  REV01      2GB      128MB      NA         NA               NA                                 
TE0803-02-04EV-1EB 4ev_4gb    REV02      4GB      128MB      NA         NA               NA                                 
TE0803-02-04EV-1E3 4ev_4gb    REV02      4GB      128MB      NA         1 mm connectorsNA                                 
TE0803-02-04EG-1E3 4eg_4gb    REV02      4GB      128MB      NA         1 mm connectorsNA                                 
TE0803-03-2AE11-A  2cg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-2BE11-A  2eg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-3AE11-A  3cg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-3BE11-A  3eg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-4AE11-A  4cg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-4BE11-A  4eg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-4BE21-L  4eg_4gb    REV03      4GB      128MB      NA         1 mm connectorsNA                                 
TE0803-03-4BI21-A  4eg_i_4gb  REV03      4GB      128MB      NA         NA               NA                                 
TE0803-03-4DE11-A  4ev_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-4DE21-L  4ev_4gb    REV03      4GB      128MB      NA         1 mm connectorsNA                                 
TE0803-03-4GE21-L  4eg_2_4gb  REV03      4GB      128MB      NA         1 mm connectorsNA                                 
TE0803-03-5DE11-A  5ev_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-5DI21-A  5ev_i_4gb  REV03      4GB      128MB      NA         NA               NA                 
TE0803-03-3RI21-A  3eg_li_4gb REV03      4GB      128MB      NA         NA               NA                                 
TE0803-03-3BI21-A  3eg_i_4gb  REV03      4GB      128MB      NA         NA               NA                                 
TE0803-03-4DI21-L  4ev_i_4gb  REV03      4GB      128MB      NA         1 mm connectorsNA                                 
TE0803-03-4GI11-A  4eg_2i_2gb REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-4GE11-A  4eg_2_2gb  REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-4GI21-A  4eg_2i_4gb REV03      4GB      128MB      NA         NA               NA                                 
TE0803-03-5BE11-A  5eg_2gb    REV03      2GB      128MB      NA         NA               NA                                 
TE0803-03-5DI24-A  5ev_i_4gb  REV03      4GB      512MB      NA         NA               NA                                 
TE0803-03-4BI21-X  4eg_i_4gb  REV03      4GB      128MB      NA         NA               U41 replaced with diode          
TE0803-03-3BE21-A  3eg_4gb    REV03      4GB      128MB      NA         NA               NA                                 
TE0803-03-3AE10-A  3cg_0_2gb  REV03      2GB      NA         NA         NA               NA                                 
TE0803-03-3AE10-A  3cg_0_2gb  REV03      2GB      NA         NA         NA               NA      


Design supports following carriers:

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Carrier ModelNotes
TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended


Additional HW Requirements:

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Additional HardwareNotes
CoolerIt's recommended to use cooler on ZynqMP device
USB CableConnect to USB2 or better USB3 Hub for proper power supply over USB
DP MonitorOptional HW
Not all monitors are supported, also Adapter to other  Standard can make drouble.
Design was testet with  DELL U2412M
Micro USB to USB A AdapterAdapter for USB Hub
USB HUBTo connnect Mouse and Keyboard simultaneously
USB Keyboardneed for Ubuntu/Debian GUI
USB Mouseneed for Ubuntu/Debian GUI
DP Cable--
Sata DiskOptional HW
SATA CableOptional HW
PCIe CardOptional HW
ETH Cable

Optional HW
Ethernet works with DHCP, but can be setup also manually

SD Card16GB


Content

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Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration


Prebuilt

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  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Image---Generic Linux kernel binary image file
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems

      Device Tree Blob File*.dtbContains a Device Tree Blob




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Additional Sources

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titleAdditional design sources

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Prebuilt

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Notes :

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titlePrebuilt files

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File

...

File-Extension

...

Description

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Debian SD-Image

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*.img

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Debian Image for SD-Card

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

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*.mmi

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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

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SREC-File

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*.srec

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Converted Software Application for MicroBlaze Processor Systems

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titlePrebuilt files (only on ZIP with prebult content)

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File

...

File-Extension

...

Description

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Debian SD-Image

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*.img

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Debian Image for SD-Card

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

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*.mmi

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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

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SREC-File

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*.srec

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Converted Software Application for MicroBlaze Processor Systems

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Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see alsoTE Board Part Files
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
              optional "TE::pr_program_flash -swapp hello_te0820" possible
  4. Copy image.ub on SD-Card
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section 43680037
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device
  4. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequ:...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Control:
  • Monitoring:

...

anchorFigure_VHM
titleVivado Hardware Manager

System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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anchorFigure_BD
titleBlock Design

PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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titlePS Interfaces

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Type

File

Note

File-Extension

DDR

Description

QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
UART0MIO
GPIO0MIO
SWDT0..1TTC0..3
GEM3MIO
USB0MIO

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]
BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Image---Generic Linux kernel binary image file
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Device Tree Blob File*.dtbContains a Device Tree Blob


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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NoteNotes :
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

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FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see alsoTE Board Part Files
      1. Important: Use Board Part Files, which ends with *_tebf0808
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (bl31.elf, uboot.elf , Image and system.dtb) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux/
      2. Execute the script file for Debian/Ubuntu
  7. Add Linux files (bl31.elf, uboot.elf , Image and system.dtb) to prebuilt folder
    1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
  9. Preparing SD card for SD Filesystem and hard disk for HD Filesystem → See Programming section

Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Not used in this example.

SD

  1. Format the SD Card with SD Card Formatter or other tool
  2. Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
  3. It will automatically in BOOT directory two DTB file generated
    1. system_sd.dtb : This file ist used , if the root file system is located on SD card.
    2. system_harddisk.dtb : This file ist used , if the root file system is located on hard disk.
    3. Note: To use one of the DTB files, this file must be renamed to system.dtb
  4. Rename the system_sd.dtb file in BOOT directory to system.dtb
  5. Copy Petalinux  Image (not use image.ub), system.dtb and Boot.bin files on SD-Card.
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  6. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  7. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section TE0803 StarterKit#Programming
  2. Connect UART USB (JTAG XMOD)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  5. (Optional) Connect Sata Disc
  6. (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
  7. (Optional) Connect Network Cable
  8. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
  4. Debian Desktop
    1. Use connected mouse + keyboard for interaction with GUI
    2. Start the GUI with the command : startx
    3. Web Browser Dillo open console and type dillo or use browser
    4. open console and start video or audio with "mplayer <video or audio file>"
  5. Ubuntu Desktop
    1. Use connected mouse + keyboard for interaction with GUI
    2. Start the GUI with the command : startx
    3. Web Browser Mozilla firefox can be used.
    4. Audio or Vider file can also be performed directly in GUI


Hard Disk (optional)

To locate root file system on Hard disk:

  1. Plug in SD Card that you have prepared mit root file system
  2. Plug in Hard Disk in Sata port on the carrier board
  3. Format the hard disk by the following command:
    1. mkfs.ext4 /dev/sda
  4. Edit the fstab file in directory /etc/ to mount hard disk by the following commands:
    1. mkdir /media/harddisk
    2. nano /etc/fstab
    3. Add this line to the fstab file and save it : /dev/sda  /media/harddisk/   defaults  0  3
    4. Reboot
  5. Copy entire root file system in direcroty ROOTFS from SD card to hard disk by the following commands:
    1. cd /media/ROOTFS
    2. cp -r ./ /media/harddisk
  6. Edit the fstab file in directory /media/harddisk/etc/ by the following commands and save it:
    1. nano /media/harddisk/etc/fstab
    2. Edit this line to the fstab file : /dev/sda  /media/harddisk/   defaults  0  1
    3. Comment this line: #/dev/mmcblk1p2   /media/ROOTFS     defaults  0  1
  7. Shutdown the system
  8. Format the SD card
  9. Rename the Device Tree Blob file system_harddisk.dtb to system.dtb
  10. Copy the following files to SD Card:
    1. Image
    2. BOOT.bin
    3. system.dtb
  11. Plug in the SD Card and turn on the system

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequ:...


System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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Image Added

PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

Scroll Title
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titlePS Interfaces

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TypeNote
DDR
QSPIMIO
SD0MIO
SD1MIO
I2C0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3
GEM3MIO
USB0MIO/GTP
SATAGTP
DisplayPortEMIO/GTP
PCIeMIO/GTP
CAN0EMIO
PJTAG0MIO


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc

# system controller ip
#LED_HD SC0 J3:31
#LED_XMOD SC17 J3:48 
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S  SC16 J3:46 B26_L1_N

set_property PACKAGE_PIN G14 [get_ports BASE_sc0]
set_property PACKAGE_PIN D15 [get_ports BASE_sc5]
set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A14 [get_ports BASE_sc12]
set_property PACKAGE_PIN B14 [get_ports BASE_sc13]
set_property PACKAGE_PIN F13 [get_ports BASE_sc14]
set_property PACKAGE_PIN G13 [get_ports BASE_sc15]
set_property PACKAGE_PIN A15 [get_ports BASE_sc16]
set_property PACKAGE_PIN B15 [get_ports BASE_sc17]
set_property PACKAGE_PIN J14 [get_ports BASE_sc18]
set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

# Audio Codec
#LRCLK		  J3:49 
#BCLK		    J3:51 
#DAC_SDATA	J3:53 
#ADC_SDATA	J3:55 
set_property PACKAGE_PIN L13 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN L14 [get_ports I2S_bclk ]
set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

Software Design - Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • OTG+PCIe Reset over MIO
    • I2C MUX for EEPROM MAC

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card

Changes:

  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
  • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
  • # CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set

  • CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"

  • CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT is not set

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set

  • CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT=y

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set

  • CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"

  • CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set

  • CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set

  • # CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set

  • CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="Image"

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

  • CONFIG_I2C_EEPROM=y

  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

  • CONFIG_SYS_I2C_EEPROM_ADDR=0x50

  • CONFIG_SYS_I2C_EEPROM_BUS=2

  • CONFIG_SYS_EEPROM_SIZE=256

  • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

  • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

  • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

  • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
  chosen {
    	xlnx,eeprom = &eeprom;
		bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M";
		/* notes: root=/dev/mmcblk1p2 for SD and root=/dev/sda for hard disk will be changed automatically  by executing debian/ubuntu script*/
  };
};

/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h
*/

/* default */

/* SD */

&sdhci1 {
	disable-wp;
	no-1-8-v;

};




/* USB  */


&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    phys = <&lane1 4 0 2 100000000>;
    maximum-speed = "super-speed";
};

/* ETH PHY */

&gem3 {
	phy-handle = <&phy0>;
	phy0: phy0@1 {
		device_type = "ethernet-phy";
		reg = <1>;
	};
};

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* I2C */

&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c@2 { // PCIe
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // SFP1 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 {// SFP2 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // TEBF0808 EEPROM
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
            eeprom: eeprom@50 {
	            compatible = "atmel,24c08";
	            reg = <0x50>;
	          };
        };
        i2c@6 { // TEBF0808 FMC  
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // TEBF0808 USB HUB
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0808 PMOD P1
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
			/*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
			*/
        };
        i2c@2 { // TEBF0808 Firefly A
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // TEBF0808 Firefly B
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 or SI5345
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { //TEBF0808 CPLD
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // TEBF0808 PMOD P3
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
};




Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

  • CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

File System will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)

Applications

Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)

Template location: ./sw_lib/sw_apps/

...

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • No changes.

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • No changes.

Change platform-top.h:

...

languagejs

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


Kernel

Start with petalinux-config -c kernel

Changes:

  • No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • No changes.

Applications

See: \os\petalinux\project-spec\meta-user\recipes-apps\

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

...

General documentation how you work with these project will be available on Si5338

...

File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

...

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Description

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dateFormatyyyy-MM-dd

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infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
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Page info
infoTypeModified by
typeFlat

  • change list2019.2 release
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
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