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Scroll Title
anchorFigure_OV_MC
titleTE0821 main components


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draw.io Diagram
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diagramNameTE0821_OV_MC
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  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. B2B connector Samtec Razor Beam, JM1
  9. Green User LED, D2
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

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Scroll Title
anchorTable_SIP_I2C
titleAddress table of the I2C bus slave devices

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I2C DeviceI2C AddressNotes

Si5338A PLL

0x70-
EEPROM0x50-


MIO Pins

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idComments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3, SPI_SCK

J2QSPI


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Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.

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FPGA BankSchematicVoltageNote
24 HDVCCO_HD24_24Variable Max voltage 3.3V
25 HD
Variable Max voltage 3.3V
26 HDVCCO_HD25_26Variable Max voltage 3.3V
44 HDVCCO_HD24_44VariableMax voltage 3.3V
65 HP

VCCO_65

VariableMax voltage 1.8V
66 HPVCCO_661.8V
500 PSMIOVCCO_PSIO0_5001.8V

501 PSMIO

VCCO_PSIO1_501

3.3V


502 PSMIOVCCO_PSIO2_5021.8V
503 PSCONFIGVCCO_PSIO3_5031.8V
504 PSDDRDDR_1V21.2V



Board to Board Connectors

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