Page History

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• SoC/FPGA
  • Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784I
    
    • ZU3EG, 784 Pin Packages
    • Application Processor: Quad-Core ARM Cortex-A53 MPCore
    • Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
    • Graphics Processor: Mali-400 MP2
• RAM/Storage
  • 2 GByte DDR4 SDRAM, 32-Bit databus-width
  • 128 MByte QSPI boot Flash in dual parallel mode
  • 8 GByte e.MMC Memory (up to 64 GByte)
  • MAC address serial EEPROM with EUI-48 node identity
• On Board
  
  • Graphic Processing Unit (GPU) :Mali-400 MP2
• Interface
  • PCI Express interface version 2.1 compliant
  • SATA 3.1 specification compliant interface

  • DisplayPort source-only interface with video resolution up to 4k x 2k

  • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • 1 GB/s serial GMII interface
  • Hi-speed USB2 ULPI transceiver with full OTG support
  • 34 x High Performance und 96 x High Density PL I/Os
  • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
  • 4 x serial PS GTR transceivers
  • Rugged for shock and high vibration
• Power
  • All power supplies on board
• Dimension
  • 40 x 50 mm

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1. Xilinx Zynq UltraScale+ XCZU3EG, U1
2. Red LED (ERR_OUT), D3
3. Green LED (ERR_STATUS), D4
4. Red LED (DONE), D1
5. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
6. 8Gb DDR4, U2-U3
7. 512 Mbit QSPI flash memory, U7-U17
8. B2B connector Samtec Razor Beam, JM1
9. Green User LED, D2
10. Programmable clock generator, U10
11. USB2.0 Transceiver,  U18
12. B2B connector Samtec Razor Beam, JM3
13. B2B connector Samtec Razor Beam, JM2
14. 8 GByte eMMC memory, U6
15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

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Configuration Signals

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Please refer to the TE0821 CPLD-Bootmode.

Signals, Interfaces and Pins

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