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  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. B2B connector Samtec Razor Beam, JM1
  9. Green User LED, D2
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Scroll Title
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titleGeneral PL I/O to B2B connectors information

Scroll Table Layout
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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
24HDJM224x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
25HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
26HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
44HDJM224x I/O, 12x  LVDS PairsVariableMax voltage 3.3V
65

HP

JM2

18x I/O, 9x LVDS Pairs

VariableMax voltage 1.8V

65

HP

JM3

16x I/O, 8x LVDS Pairs

Variable

Max voltage 1.8V
505GTRJM316x I/O, 8x LVDS Pairs-4x lanes
505GTR CLKJM31x Diff Clock-

501

MIO

JM1

15 I/O

3.3V



For detailed information about the pin-out, please refer to the Pin-out table.

JTAG Interface

JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JM2.

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Scroll Title
anchorTable_SIP_CPLD
titleSystem Controller CPLD special purpose pins

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Pin NameModeFunctionDefault Configuration
EN1InputPower Enable

No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management

PGOODOutputPower GoodOnly indirect used for power status, see CPLD description
NOSEQ--No used for Power sequencing, see CPLD description
RESINInputReset

Active low reset, gated to POR_B

JTAGENInputJTAG SelectLow for normal operation, high for CPLD JTAG access


Please check the entire information at TE0821 CPLD.

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14). 

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