...
| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | B2B Connector |
|
|---|
| TMS | JM2-93 |
| | TDI | JM2-95 |
| | TDO | JM2-97 |
| | TCK | JM2-99 |
JTAG_EN |
System Controller CPLD I/O Pins
| Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD |
|
MGT Lanes
| Scroll Title |
|---|
| anchor | Table_SIP_MGT |
|---|
| title | MGT Lanes Connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Lane | B2B Connector |
|
|---|
| TMS | JM2-93 |
| | TDI | JM2-95 |
| | TDO | JM2-97 |
| | TCK | JM2-99 |
| | JTAGSEL | JM1-89 | Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD |
|
System Controller CPLD I/O Pins
| Page properties |
|---|
|
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
|---|
| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
|
| Scroll Title |
|---|
| anchor | Table_OBP_SC |
|---|
| title | System Controller CPLD special purpose pin description |
|---|
|
|
| Page properties |
|---|
|
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
Example:
| MIO Pin | Connected to | B2B | Notes |
|---|
| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
| Scroll Title |
|---|
| anchor | Table_OBP_SC |
|---|
| title | System Controller CPLD special purpose pin description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| CPLD Pin | Connected to | B2B | Notes |
|---|
| Scroll Title |
|---|
| anchor | Table_OBP_SPI |
|---|
| title | SPI Interface |
|---|
|
| scroll-tablelayout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
FPGA (U2)| Signal Name | SPI Pin (U4) | Notes | SC_SPI_ENABLE | |
...
| Page properties |
|---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...
Notes :
...
| Connected to | B2B | Notes |
|---|
| TDO - 1 | TDO | JM2 - 97 |
| | TDI - 32 | TDI | JM2 - 95 |
| | TCK - 30 | TCK | JM2 - 99 |
| | TMS - 29 | TMS | JM2 - 93 |
| | JTAGENB - 26 | JTAGSEL | JM1 - 89 |
| - 11 | SC_EN1 | JM1 - 28 |
| | - 12 | SC_PGOOD | JM1 - 30 |
| | - 14 | SC_nRST | JM2 - 18 |
| | - 17 | NOSEQ | JM1 - 7 |
|
|
SPI Pins
| Scroll Title |
|---|
| anchor | Table_OBP_SPI |
|---|
| title | On board peripheralsSPI Interface |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Chip/Interface | Designator | Notes |
|---|
Quad SPI Flash Memory
| Page properties |
|---|
|
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
...
| anchor | Table_OBP_SPI |
|---|
| title | Quad SPI interface MIOs and pins |
|---|
| FPGA Pin (U2) | Signal Name | SPI Pin (U3) | Notes |
|---|
| SCK_3 - E6 | SPI_SCK | B2 |
| | SS_3 | SPI_SS | C2 |
| | SDO_3 | SPI_SDO | D3 |
| | SDI_3 | SPI_SDI | D2 |
| | SPI_EN_3 | SPI_EN | - |
|
|
On-board Peripherals
| Page properties |
|---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
| Page properties |
|---|
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| Scroll Title |
|---|
| anchor | Table_OBP |
|---|
| title | On board peripherals |
|---|
|
...
| Scroll Title |
|---|
| anchor | Table_OBP_RTC |
|---|
| title | I2C interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| MIO Pin | Schematic | U? Pin | Notes |
|---|
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_RTC |
|---|
| title | I2C Address for RTC |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| MIO Pin | I2C Address | Designator | Notes |
|---|
...
| Chip/Interface | Designator | Notes |
|---|
| CPLD | U1 |
| | Ethernet | U7 |
| | EEPROM | U10 |
| | FLASH | U3 |
| | Oscillators | U4...5, U12 |
| | LPDDR4 | U6 |
| | USB | U11 |
|
|
SPI Flash Memory
| Page properties |
|---|
|
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TEM0007 is equipped with a MT25QU512ABB8E12-0SIT flash memory chip, U3, which provided storage for FPGA configuration files. After configuration, the remaining free memory can be used for application data storage.
| Scroll Title |
|---|
| Scroll Title |
|---|
| anchor | Table_OBP_EEPSPI |
|---|
| title | I2C EEPROM SPI Flash interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
MIO | Polarfire SoC Pin | Schematic |
|---|
U?? |
scroll |
title |
| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C address for EEPROM |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| MIO Pin | I2C Address | Designator | Notes |
|---|
LEDs
| SPI_SCK | CLK - B2 |
| | SS_3 - G7 | SPI_SS | CS# - C2 |
| | SDO_3 - F7 | SPI_SDO | DI/IO0 - D3 |
| | SDI_3 - H10 | SPI_SDI | DO/IO1 - D2 |
| | SPI_EN_3 - H11 | SPI_EN | - |
|
|
EEPROM
There is a 2 Kbit EEPROM provided on the module TEM0007 with a pre-programmed globally unique MAC.
| Scroll Title |
|---|
| anchor | Table_OBP_LEDEEP |
|---|
| title | On-board LEDsI2C EEPROM interface MSSIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Designator| MSSIO Pin | ColorSchematic | Connected to | Active Level | Note |
|
DDR3 SDRAM
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
Ethernet
| U10 Pin | Notes |
|---|
| 26 | I2C_SCL | SCL - 1 |
| | 27 | I2C_SDA | SDA - 3 |
|
|
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C address for EEPROM |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MSSIO Pin | I2C Address | Designator | Notes |
|---|
| 26...27 | 0x50 | U10 |
|
|
LEDs
| Scroll Title |
|---|
| anchor | Table_OBP_LED |
|---|
| title | On-board LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Color | Connected to | Active Level | Note |
|---|
|
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|
|
|
|
|
|
|
|
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LPDDR4 SDRAM
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEM0007 SoM has a one GByte volatile LPDDR4 SDRAM IC for storing user application code and data.
- Part number: IS43LQ32256A-062BLI
- Supply voltage: +1.8 V / +1.1 V
- Speed: 1600 MHz
- Temperature: Industrial (-40°C to +85°C)
USB PHY
Hi-speed USB ULPI PHY (U11) is provided with USB3320 from Microchip. The ULPI interface is connected to the Polarfire SoC via MSSIO14...25 bank 2. The I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U12).
| Scroll Title |
|---|
| anchor | Table_OBP_USB |
|---|
| title | USB PHY to Polarfire SoC connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Bank 2 | Signal Name | USB | Signal Description |
|---|
U2 - G4 | OTG-STP | U11 - 29 | Stop | | U2 - G5 | OTG-NXT | U11 - 2 | Next | U2 - F1 | OTG-DIR | U11 - 31 | Direction | | U2 - G2 | OTG-CLK | U11 - 1 | Clock | | U2 - F2 | OTG_DATA0 | U11 - 3 | ULPI bi-directional data bus | | U2 -E1 | OTG_DATA1 | U11 - 4 | ULPI bi-directional data bus | | U2 -G3 | OTG_DATA2 | U11 - 5 | ULPI bi-directional data bus | | U2 -F5 | OTG_DATA3 | U11 - 6 | ULPI bi-directional data bus | | U2 - D1 | OTG_DATA4 | U11 - 7 | ULPI bi-directional data bus | | U2 -D2 | OTG_DATA5 | U11 - 9 | ULPI bi-directional data bus | | U2 -F6 | OTG_DATA6 | U11 - 10 | ULPI bi-directional data bus | | U2 - F3 | OTG_DATA7 | U11 - 13 | ULPI bi-directional data bus |
|
Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).
| Scroll Title |
|---|
| anchor | Table_OBP_ETH |
|---|
| title | Ethernet PHY to Zynq Polarfire SoC connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
CAN Transceiver
...
| anchor | Table_OBP_CAN |
|---|
| title | CAN Tranciever interface MIOs |
|---|
...
U2 - N6 | SGMII0_IN_P | U7 - 1 | SGMII Data Positive | | U2 - N7 | SGMII0_IN_N | U7 - 2 | SGMII Data Negativ | U2 - L5 | SGMII0_OUT_P | U7 - 4 | SGMII Data Positive | | U2 - L6 | SGMII0_OUT_N | U7 - 5 | SGMII Data Negativ |
|
System Controller CPLD
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Oscillators
...
| Scroll Title |
|---|
| anchor | Table_OBP_CLK |
|---|
| title | Osillators |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Description | Frequency | Note |
|---|
| U4 | MSS REFCLK | 125 MHz |
| | U5 | SERDES CLK | 125 MHz |
| | U12 | USB | 52 MHzKHz |
|
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|
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|
Power and Power-On Sequence
...