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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General SoC I/O to B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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0 | JM2 | 18 | 1.2 V / 1.35 V / 1.5 V / 1.8 V | HSIO dependent on VCCIOD | 0 | JM3 | 16 | 1.2 V / 1.35 V / 1.5 V / 1.8 V | HSIO dependent on VCCIOD | 1 | JM1 | 48 | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | GPIO dependent on VCCIOB | 1 | JM2 | 36 | 1.2 V / 1.5 V / 1.8 V / 2.5 V / 3.3 V | GPIO dependent on VCCIOB | 4 | JM1 | 6 (14) | 3.3 V | MSSIO | 4 | JM1 | 6 | 3.3 V | SDIO - MSSIO | 4 | JM1 | 2 | 3.3 V | UART - MSSIO | MSSIO (14 signals including UART and SDIO) | 5 | JM3 | 4 | - | SGMII (1 pairs pair for TX / 1 pairs pair for RX) | 5 | JM3 | 16 | - | SERDES (4 pairs for TX / 4 pairs for RX) | 5 | JM3 | 4 | - | SERDES CLK (2 pairs for RX) |
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Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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JTAG Signal | B2B Connector |
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TMS | JM2-93 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TCK | JM2-99 |
| JTAGSEL | JM1-89 | Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD |
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UART Interface
The UART interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
Scroll Title |
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anchor | Table_SIPOBP_MGTUART |
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title | MGT Lanes ConnectionUART interface description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Lane ConnectorTMSJM293TDIJM295JM2TDO | 97TCKJM299JTAGSEL | JM1-89 | Pulled Low: Microsemi Polarfire SoC Pulled High: Lattice MachXO CPLD | |
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SDIO Interface
The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.
Scroll Title |
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anchor | Table_OBP_SDIO |
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title | SDIO interface description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank 4 | Connected to | B2B | Notes |
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MSSIO0 - J1 | SDIO_CLK | JM1 - 27 |
| MSSIO1 - K5 | SDIO_CMD | JM1 - 25 |
| MSSIO2 - H1 | SDIO_DAT0 | JM1 - 23 |
| MSSIO3 - J4 | SDIO_DAT1 | JM1 - 21 |
| MSSIO4 - K4 | SDIO_DAT2 | JM1 - 19 |
| MSSIO5 - J7 | SDIO_DAT3 | JM1 - 17 |
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MSSIO
Six MSSIOs are connected from the Polarfire SoC to the B2B connector.
Scroll Title |
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anchor | Table_OBP_MSSIO |
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title | MSSIO interface description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank 4 | Connected to | B2B | Notes |
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MSSIO6 - K3 | MIO0 | JM1 - 97 |
| MSSIO7 - H4 | MIO1 | JM1 - 91 |
| MSSIO8 - J6 | MIO2 | JM1 - 99 |
| MSSIO9 - H6 | MIO3 | JM1 - 87 |
| MSSIO10 - J3 | MIO4 | JM1 - 95 |
| MSSIO13 - J2 | MIO5 | JM1 - 93 |
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SGMII Interface
The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.
Scroll Title |
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anchor | Table_OBP_SGMII |
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title | SGMII interface description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank 5 | Connected to | B2B | Notes |
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U2 - N8 | SGMII1_OUT_N | JM3 - 1 |
| U2 - M7 | SGMII1_OUT_P | JM3 - 3 |
| U2 - K7 | SGMII1_IN_N | JM2 - 2 |
| U2 - K6 | SGMII1_IN_P | JM2 - 4 |
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MGT Lanes
There are four MGT (Multi Gigabit Transceiver) lanes and two two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:
Scroll Title |
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anchor | Table_SIP_MGT |
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title | MGT Lanes Connection |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Lane | Schematic | B2B | Note |
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0 | XCVR_RX0_P | JM3-26 |
| 0 | XCVR_RX0_N | JM3-28 |
| 0 | XCVR_TX0_N | JM3-25 |
| 0 | XCVR_TX0_P | JM3-27 |
| 1 | XCVR_RX1_P | JM3-20 |
| 1 | XCVR_RX1_N | JM3-22 |
| 1 | XCVR_TX1_P | JM3-19 |
| 1 | XCVR_TX1_N | JM3-21 |
| 2 | XCVR_RX2_P | JM3-14 |
| 2 | XCVR_RX2_N | JM3-16 |
| 2 | XCVR_TX2_P | JM3-13 |
| 2 | XCVR_TX2_N | JM3-15 |
| 3 | XCVR_RX3_P | JM3-8 |
| 3 | XCVR_RX3_N | JM3-10 |
| 3 | XCVR_TX3_P | JM3-7 |
| 3 | XCVR_TX3_N | JM3-9 |
| CLK | XCVR_CLK0_P | JM3-33 |
| CLK | XCVR_CLK0_P | JM3-31 |
| CLK | XCVR_CLK1_P | JM3-32 |
| CLK | XCVR_CLK1_N | JM3-34 |
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Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC.
Scroll Title |
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anchor | Table_OBP_ETH |
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title | Gigabit Ethernet pin description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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ETH Pin | Connected to | B2B | Notes |
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MDIP[0] - 28 | PHY_MDI0_P | JM1 - 4 |
| MDIN[0] - 27 | PHY_MDI0_N | JM1 - 6 |
| MDIP[1] - 24 | PHY_MDI1_P | JM1 - 10 |
| MDIN[1] - 23 | PHY_MDI1_N | JM1 - 12 |
| MDIP[2] - 22 | PHY_MDI2_P | JM1 - 16 |
| MDIN[2] - 21 | PHY_MDI2_N | JM1 - 18 |
| MDIP[3] - 18 | PHY_MDI3_P | JM1 - 22 |
| MDIN[3] - 17 | PHY_MDI3_N | JM1 - 24 |
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System Controller CPLD I/O Pins
The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
Page properties |
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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Scroll Title |
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anchor | Table_OBP_SC |
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title | System Controller CPLD special purpose pin description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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CPLD Pin | Connected to | B2B | Notes |
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TDO - 1 | TDO | JM2 - 97 |
| TDI - 32 | TDI | JM2 - 95 |
| TCK - 30 | TCK | JM2 - 99 |
| TMS - 29 | TMS | JM2 - 93 |
| JTAGENB - 26 | JTAGSEL | JM1 - 89 |
| - 11 | SC_EN1 | JM1 - 28 |
| - 12 | SC_PGOOD | JM1 - 30 |
| - 14 | SC_nRST | JM2 - 18 | - 17 | NOSEQ | JM1 - 7 |
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SPI Pins
| SC_nRST | JM2 - 18 |
| - 17 | NOSEQ | JM1 - 7 |
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USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).
Scroll Title |
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anchor | Table_OBP_SPIUSB |
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title | SPI InterfaceGeneral Overview of the USB PHY Signals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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PHY Pin | Connected to | B2B | Notes |
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DP - 18, | OTG-D_P | JM3 - 47 | USB data line | DM - 19 | OTG-D_N | JM3 - 49 | USB data line | CPEN - 17 | VBUS_EN | JM3 - 53 | External USB power switch | VBUS - 22 | VBUS | JM3 - 55 |
| ID - 23 | ID | JM3 - 51 |
FPGA Pin (U2) | Signal Name | SPI Pin (U3) | Notes |
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SCK_3 - E6 | SPI_SCK | B2 | SS_3 | SPI_SS | C2 | SDO_3 | SPI_SDO | D3 | SDI_3 | SPI_SDI | D2 | SPI_EN_3 | SPI_EN | -
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On-board Peripherals
Page properties |
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Scroll Title |
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anchor | Table_OBP |
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title | On board peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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CPLD | U1 |
| Ethernet Ethernet | U7 |
| EEPROM | U10 |
| FLASH | U3 |
| Oscillators | U4...5, U12 |
| LPDDR4 | U6 |
| USB | U11 |
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Scroll Title |
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anchor | Table_OBP_USB |
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title | USB PHY to Polarfire SoC connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Bank 2 | Signal Name | USB | Signal Description |
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U2 - G4 | OTG-STP | U11 - 29 | Stop | U2 - G5 | OTG-NXT | U11 - 2 | Next | U2 - F1 | OTG-DIR | U11 - 31 | Direction | U2 - G2 | OTG-CLK | U11 - 1 | Clock | U2 - F2 | OTG_DATA0 | U11 - 3 | ULPI bi-directional data bus | U2 -E1 | OTG_DATA1 | U11 - 4 | ULPI bi-directional data bus | U2 -G3 | OTG_DATA2 | U11 - 5 | ULPI bi-directional data bus | U2 -F5 | OTG_DATA3 | U11 - 6 | ULPI bi-directional data bus | U2 - D1 | OTG_DATA4 | U11 - 7 | ULPI bi-directional data bus | U2 -D2 | OTG_DATA5 | U11 - 9 | ULPI bi-directional data bus | U2 -F6 | OTG_DATA6 | U11 - 10 | ULPI bi-directional data bus | U2 - F3 | OTG_DATA7 | U11 - 13 | ULPI bi-directional data bus |
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Gigabit Ethernet
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U8).
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