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  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2EG, ZU3EG, ZU4EG, ZU5EGZU2 ...ZU5, *
    • Engine:  G (General Purpose) EG, CG, EV, *
    • Speed: -1 (slowest), -1L, -2, -2L, 3, *, **
    • Temperature: I, E, *, **Temperature: Industrial (-40 ~ 85 °C)
  • RAM/Storage
    • 2 GByte 2x  DDR4 SDRAM, 32-Bit databus-width
      • Data Width: 16 Bit
      • Size: 8 Gb, *
      • Speed: 2400 Mbps, ***
    • 2x 128 MByte QSPI boot Flash in dual parallel mode
      • Data Width: 8 Bit
      • Size: 512 Mb Gb, *
    • 1x e.MMC Memory
      • Data Width: 16 Bit
      • Size: 8 Gb, *
      8 GByte e.MMC Memory (up to 64 GByte)
    • MAC address serial EEPROM with EUI-48 node identity
  • On Board
    • Graphic Processing Unit (GPU) :Mali-400 MP2
    • Lattice MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 4x LEDS
  • InterfaceInterface
    • PCI Express interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

      • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
    • Hi-speed USB2 ULPI transceiver with full OTG support
    • 34 x High Performance und High Performance (HP) und 96 x High Density PL I/Os
    • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
    • 4 x serial PS GTR transceiversRugged for shock and high vibration
      • PCI Express interface version 2.1 compliant
      • SATA 3.1 specification compliant interface

      • DisplayPort source-only interface with video resolution up to 4k x 2k

      • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • Power
    • All power supplies regulators on board
  • Dimension
    • 40 x 50 mmx 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTE0821 main components


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  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps energy efficient ethernet transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. Green User LED, D2
  9. B2B connector Samtec Razor Beam, JM1
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

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Scroll Title
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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Dual QSPI Flash Memory

Not programmed


eMMC Memory

Not programmed


Programmable Clock GeneratorNot programmed
CPLD (LCMXO2-256HC)???? FirmwareProgrammedTE0821 CPLD


Configuration Signals

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titleBoot process.

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MODE Pin

Boot Mode
Low

QSPI

HighSD Card


Please refer to the TE0821 CPLD.


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titleReset process.

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Signal

B2BI/ONote

EN

JM1-28InputCPLD Enable Pin

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Signals, Interfaces and Pins

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titleModule power rails.

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Power Rail Name

B2B JM1 Pin

B2B JM2 Pin

B2B JM3 Pin

Direction

Notes
VIN

1, 3, 5

2, 4, 6, 8-InputSupply voltage from the carrier board
3.3V-10, 12-OutputInternal 3.3V voltage level
VCCO_HD25_269,11
-Input0 to 3.3V Voltage
3.3VIN13, 15--InputSupply voltage from the carrier board
1.8V39--OutputInternal 1.8V voltage level
JTAG VREF-91-OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_HD24_
64
44-7, 9-Input
High performance I/O bank voltage
0 to 3.3V Voltage
VCCO_65-5
InputHigh performance I/O bank voltage
-Input0 to 1.8V Voltage
PSBATT79-
VCCO_669, 11
-Input
High performance I/O bank voltage
1.2 to 1.5V Voltage


Bank Voltages

Scroll Title
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titleZynq SoC bank voltages.

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FPGA BankSchematicVoltageNote
Bank 24 HDVCCO_HD24_24Variable Max voltage 3.3V
Bank 25 HD
Variable Max voltage 3.3V
Bank 26 HDVCCO_HD25_26Variable Max voltage 3.3V
Bank 44 HDVCCO_HD24_44VariableMax voltage 3.3V
Bank 64 HPVCCO_64N.CNot Connected
Bank 65 HP

VCCO_65

VariableMax voltage 1.8V
Bank 66 HPVCCO_661.8V
Bank 500 PSMIOVCCO_PSIO0_5001.8V

Bank 501 PSMIO

VCCO_PSIO1_501

3.3V


Bank 502 PSMIOVCCO_PSIO2_5021.8V
Bank 503 PSCONFIGVCCO_PSIO3_5031.8V
Bank 504 PSDDRDDR_1V21.2V


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titlePS absolute maximum ratings

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13.630 DS925 and TPS27082L datasheetPS _PSIO3630PS 5_PSIO 20HP
DescriptionMinMaxUnitNotes

VIN supply voltage

-0.3

7

V

See EN6347QI and TPS82085SIL datasheets3.3VIN supply
3.3VIN supply voltage-0.13.630VXilinx DS925 and TPS27082L datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.630VXilinx document DS925
PS I/O input voltage-0.5VCCO_PSIO + 0.55VXilinx document DS925
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS925
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925HP
HD I/O bank supply voltage, VCCO-0.53.4VXilinx document DS925
HD I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC datasheet


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Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.36VSee TPS82085S datasheet
3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925
HP I/O banks supply voltage, VCCO0.9501.9VXilinx document DS925
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
HD I/O banks supply voltage, VCCO1.143.4VXilinx document DS925
HD I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range


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