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| Any other usage of the SPI bus is neither supported nor recommended. |
SPI bus for configuration
The SPI bus is used for configuration in two ways by default:
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The PROM file (containing the FPGA configuration bitstream) can be written to the SPI serial Flash memory (slave) also through the SPI pins of B2B connector J5 (attached device set to master mode). In this case, the FPGA shall be turned off or three-stated to release its shared SPI pins and the USB FX2 microcontroller shall three-state (Z = high impedance) its shared SPI pins.
SPI bus for operation
A plurality of usage combinations of the SPI bus during operation is made available to the user as suggested in Table B below.
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SPI Header Connector J3
SPI signals are made available on the dedicated header J3 accessible through an SPI programmer with flying leads as described in the table below.
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Overview
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