...
TE0320 and TE0300 module: FPGA Spartan3A and Spartan3E
Only SPI_buswidth = 1 is supported by TE0300 and TE0320 module.
| Scroll Title |
|---|
| title | FPGA SPI Configuration Interface (DATA) Pins: PD[7:4] for TE0300 and TE0320 module |
|---|
|
Only SPI_buswidth = 1 is supported by TE0300 and TE0320 module | Pin Name SPIFPGA
FPGA Direction | Pin Name FX2
FX2 direction | Description | During Configuration | After Configuration |
|---|
SPI/S | CSO_B of Spartan3 Output | PD4 Output when
the FPGA is
powerd off by
spi functions (1) | Master SPI Chip Select Output
Active Low.
Connect to the SPI Flash PROM’s
Slave Select input. Chip select: When the S# input
signal is HIGH, the device is deselected
and DQ1 is at HIGH impedance.
Unless an internal PROGRAM, ERASE,
or WRITE STATUS REGISTER cycle
is in progress, the device will be in
the standby power mode (not the
DEEP POWERDOWN mode).
Driving S# LOW enables the device,
placing it in the active power mode.
After power-up, a falling edge on S#
is required prior to the start of any
command. | If HSWAP
or PUDC_B =1, connect this signal
to a 4.7 kΩ pull-up resistor
to 3.3V. | Drive CSO_B High after configuration to disable the SPI Flash and reclaim the MOSI, DIN, and CCLK pins. Optionally, re-use this pin and MOSI, DIN, and CCLK to continue communicating with SPI Flash. | | SPI/C | CCLK Output | PD5 Output when
the FPGA is
powerd off by
spi functions (1) | Configuration Clock. Generated by
FPGA internal oscillator.
Connect to the SPI Flash PROM’s
Slave Clock input.
Frequency controlled by ConfigRate
bitstream generator option.
If CCLK PCB trace is long or has
multiple connections, terminate this
output to maintain signal integrity. Clock: The C input signal provides the
timing of the serial interface.
Commands, addresses, or data present
at serial data input (DQ0) is latched on
the rising edge of the serial clock (C).
Data on DQ1 changes after the falling
edge of C. | Drives SPI Flash
PROM’s clock input. | User I/O. Drive High or Low if not used. | | SPI_D | MOSI Output | PD6 Output when
the FPGA is
powerd off by
spi functions (1) | Master SPI Serial Data Output Connect
to the SPI Flash PROM’s Slave
Data Input pin. Serial data: The DQ0 input signal is
used to transfer data serially into the
SPI Flash device.
It receives commands, addresses,
and the data to be programmed.
Values are latched on the rising edge
of the serial clock (C). | FPGA sends
SPI Flash memory
read commands and starting address
to the PROM’s
serial data input. | User I/O | SPI_Q | DIN Input | PD7 Input, by default (2) | Master SPI Serial Data Input Connect
to the SPI Flash PROM’s Slave Data
Output pin. Serial data: The DQ1 output signal is
used to transfer data serially out of the
SPI Flash device.
Data is shifted out on the falling edge
of the serial clock (C). | FPGA receives serial
data from SPI Falsh
PROM’s serial data
output. | User I/O |
|
...
All TE USB FX2 module (TE0630,TE0320,TE0300): FPGA Spartan6, Spartan3A and Spartan3E
...
| title | FPGA SPI Configuration Interface (CONTROL/STATUS) Pins: PD[3:0] for every TE USB FX2 module |
|---|
...
FX2_PS_EN is used to control the signal PS_EN (if the switch FX2_ON is set to on), so it is not really part of the SPI Configuration Interface.
| Scroll Title |
|---|
| title | FPGA SPI Configuration Interface (CONTROL/STATUS) Pins: PD[3:0] for every TE USB FX2 module |
|---|
|
Pin Name
Schematic | Pin Name FPGA
FPGA Direction | Pin Name FX2
FX2 direction | Description | During Configuration | After Configuration |
|---|
| FX2_PS_EN | NOT
CONNECTED | PD0 Bidirectional
Input/Output (3) | Control of signal PS_EN
if the switch FX2_ON is
set to on. Some power rails are
controlled by the USB FX2
microcontroller (FX2 μC).
At start-up, the FX2 μC
switches off some power
rails and starts up the
module in low-power mode.
After enumeration, the
FX2 microcontroller firmware
enables (switches on) the
power rails previously
disabled, if enough current
is available
from the USB bus. See Power Rails
Configuration: | If the switch FX2_ON is
set to on, FX2_PS_EN
should be High
to allow configuration
to start. | If the switch FX2_ON is
set to on, FX2_PS_EN
should be High to allow
the various components
of TE USB FX2 module
to work. | | FX2_PROG_B | PROGRAM_B
( TE0630's
Spartan 6) PROG_B
(TE0300's
Spartan 3E)
(TE0320's
Spartan 3A) Input | PD1 Bidirectional Input/Output (3)
| Program FPGA. Active Low. Active-Low asynchronous
full-chip reset. When asserted Low for
500 ns or longer,
forces the FPGA
to restart its configuration
process by clearing
configuration memory and
resetting the DONE and
INIT_B pins after
FX2_PROG_B returns High. | Must be High to allow
configuration to start. | Drive FX2_PROG_B
Low and release to
reprogram FPGA. Hold FX2_PROG_B
to force the FPGA I/O
pins into High-Z,
allowing direct
programming
access to SPI
Flash PROM pins.
| | DONE | DONE
Bidirectional I/O, Open-Drain,
or Active Use a pull-up
resistor /330Ω)
on DONE (4).
The recommendation
for DONE in the
User Guide
is to use a
330Ω pull-up.
| PD2 Input, by default (2) | Dedicated Active-High signal
indicating configuration is
complete: - 0 = FPGA not configured
- 1 = FPGA configured
Refer to the BitGen section
of UG628, Command Line
Tools User Guide for
software settings. | See FPGA configuration
process successfully
completes (DONE PIN)
page. | The FX2 μC firwmare
is able to read the
DONE PIN status
from PD2 pin (IOD2)
and the host
computer's SW
could obtain the
current value using
READ_STATUS command.
DONE PIN status
can be read from
reply[4]
(= EP1INBUF[4] =
sts_booting =
FPGA_DONE).
| INIT_B | INIT_B Open-drain bidirectional I/O Use a pull-up
resistor (4.7kΩ)
on INIT_B (4).
The recommendation | PD3 Input, by default (2) | See AR# 39582 and
AR# 35002 Initialization Indicator. Active Low. Goes Low at start of
configuration during
Initialization memory
clearing process.
Released at end of memory
clearing, when mode select
pins are sampled. The INIT pin does not have
a rise time requirement and
is
used to signal the start of
configuration as well as a
CRC,
and can also be used as
User-IO post configuration. | Active during configuration. Before the Mode pins
are sampled,
INIT_B is an input that
can be held
Low to delay configuration.
If SPI Flash PROM requires
more than 2 ms to awake after powering on,hold INIT_B Low until PROM is ready. . After the Mode pins are
sampled, INIT_B is an
open-drain active-Low output indicating whether a CRC error occurred during
configuration: - 0= CRC error
- 1= No CRC error
| User I/O. If unused in
the application, drive
INIT_B High to avoid
a floating value. Dual-Purpose:
if User I/O if
POST_CRC is not enabled. |
|
...