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Pin Name | Pin Name FPGA FPGA Direction | Pin Name FX2 | Description | During Configuration | After Configuration |
FX2_PS_EN | NOT |
CONNECTED | PD0 Bidirectional | Control of signal PS_EN |
set to on. Some power rails are controlled |
by the USB |
FX2 microcontroller. |
the FX2 |
microcontroller |
rails and |
module in low-power |
FX2 microcontroller firmware |
rails previously |
disabled, if enough |
is available See Power Rails |
set to on, FX2_PS_EN |
to allow |
to start. | If the switch FX2_ON is |
to work. | ||
FX2_PROG_B | PROGRAM_B PROG_B Input | PD1 Bidirectional Input/Output (3) |
| Program FPGA. Active Low. Active-Low asynchronous |
full-chip When asserted Low for |
500 ns |
forces the FPGA |
to restart |
process by clearing |
the DONE and |
INIT_B pins after | Must be High to allow configuration to start. | Drive FX2_PROG_B Low |
and release to reprogram |
FPGA. Hold FX2_PROG_B |
to force |
pins into |
allowing direct |
PROM pins.
| |
DONE | DONE Bidirectional I/O, Open-Drain, Use a pull-up |
resistor on DONE (4). The recommendation for DONE in the User Guide is to use a 330Ω pull-up.
| PD2 Input, | Dedicated Active-High signal |
complete:
Refer to the BitGen section of |
UG628, Command Line Tools |
User Guide for |
software settings. | See | The FX2 |
microcontroller's |
is able to read the |
PD2 pin (IOD2) |
and the host |
obtain the |
current value |
can be |
reply[4] |
(= |
sts_booting |
FPGA_DONE). | |
INIT_B | INIT_B Open-drain bidirectional I/O Use a pull-up |
resistor on INIT_B (4). The recommendation for INIT in the User Guide is to use a 4.7kΩ pull-up. | PD3 Input, | See AR# 39582 and |
Initialization Indicator. |
Active Low. Goes Low at start of configuration |
during |
Initialization memory clearing process. |
Released at end |
ofmemory clearing, when mode select |
pins are sampled. The INIT pin does not have |
a rise |
is |
used to |
configuration as |
CRC, |
and can also be |
User-IO post configuration.
| Active during |
configuration. Before the Mode pins are |
sampled, |
INIT_B is an input that |
can be held Low to delay configuration. If SPI Flash PROM requires more than 2 ms to awake after powering on,hold INIT_B Low until PROM is ready |
. After the Mode pins are sampled, INIT_B is an open-drain active-Low output |
indicating whether a CRC |
error occurred during configuration:
| User I/O. If unused in the |
application, drive INIT_B High to avoid a |
floating value. Dual-Purpose: if User I/O if |
POST_CRC is not enabled. |
Note |
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Only the status of these PD2 pin (FPGA_DONE) could be retrieved using the |
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