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Scroll Title
titleFW APIs dependencies to reference custom IP blocks
TE API Commands (FW APIs)

XPS_I2C_SLAVE
is NOT necessary

XPS_NPI_DMA
is NOT necessary		XPS_FX2
is NOT necessary

USB FX2 API Commands
type/subcase

(tick)

(warning) GET_INTERRUPT (1)

(warning) SET_INTERRUPT (1)

(tick)(tick)

MicroBlaze API Commands
(MB Commands)
type/subcase (2)

(error)  (2)

(tick)

(error) FX22MB_REG0_START_RX (3)

(error) FX22MB_REG0_START_TX (3)

(error) FX22MB_REG0_STOP (3)

(tick)

(error) FX22MB_REG0_START_RX (3)

(error) FX22MB_REG0_START_TX (3)

(error) FX22MB_REG0_STOP (3)

SPI Flash Commands
type/subcase

(tick)(tick)(tick)

LEGEND:

  • (tick) this symbol means that the reference custom IP block (in the colum) is NOT necessary for the TE API Commands (FW APIs) type/subcase of the row
  • (error) this symbol means that the reference custom IP block (in the colum) is necessary for the TE API Commands (FW APIs) type/subcase of the row

 

(1) FX2 API Commands do not require any of these reference custom IP block.

Note
titleException: SET_INTERRUPT and GET_INTERRUPT

GET_INTERRUPT command will retrieve an autoresponse byte array of x byte (maximum 32) at y I2C address (trough I2C) if the pin INT0 has been rised before and the FX2 microcontroller has been already prepared for autoresponse (SET_INTERRUPT).

SET_INTERRUPT command and GET_INTERRUPT have been originally created for XPS_I2C_SLAVE (x=12 byte and y=0x3F) to retrieve the "reply" (MB2FX2_REGs) of MB Command from MicroBlaze.

(2) MB Commands require the XPS_I2C_SLAVE reference custom IP block and a proper FX2 interrupt handler (i2c_slave_int_handler() function in interrupt.c) running on MicroBlaze.

The I2C bus is used to deliver MicroBlaze API Commands (MB Commands) to FPGA's MicroBlaze through FPGA's XPS_I2C_SLAVE custom IP block. The I2C bus is also used to retrieve the status of the MicroBlaze (SET_INTERRUPT command,  FX22MB_REG0_GETVERSION command, GET_INTERRUPT command). See  Reference Architecture Layer.

Note
MB Commands require the XPS_I2C_SLAVE reference custom IP block and a proper FX2 interrupt handler (i2c_slave_int_handler() function in interrupt.c running on MicroBlaze); the FX2 interrupt handler is called to handle the signal interrupt xps_i2c_slave_0_IP2INTC_Irpt. The i2c_slave_int_handler() function actually execute the I2C delivered MB Command; when MicroBlaze's software wants to send information to the host computer (through USB FX2 microcontroller), it should write MB2FX2_REGs of XPS_I2C_SLAVE custom IP block. The IP block will rise an interrupt request (USB_INT =1  =>pin  INT0 =1 => FPGA_INT0=1) at pin INT0. The FX2 microcontroller's FW will manage the interrupt using an "Interrupt Pin polling" function inside asuperloop ("while(1)"). The FX2 microcontroller's FW could also read the register of XPS_I2C_SLAVE custom IP block.

(3) XPS_NPI_DMA and XPS_FX2 custom IP blocks are both necessary to connect host computer's software and TE USB FX2 module's DRAM.

The MB Commands FX22MB_REG0_START_RX, FX22MB_REG0_START_TX, FX22MB_REG0_STOP are used for test. The FD[7:0] 8 bit bus is used.

Note

Write test should be executed before read test; otherwise the read test will fail.

In production, the user/developer should

  • use a Logic Architecture Layer derived (compatible) from Reference Architectrure Layer and
  • use/write some equivalent MB Command in a MicroBlaze's software derived by i2c_slave_int_handler() function in interrupt.c running on MicroBlaze

to start and stop data transmission between TE USB FX2 module's DRAM and host computer's memory.

Info

If XPS_NPI_DMA and XPS_FX2 custom IP blocks are not used (Logic Architecture Layer not compatible with Reference Architectrure Layer), the user should synthetize two equivalent IP block on the FPGA:

  • DRAM controller + "custom" logic bus connector (handshake and high data throughput connection to USB controller);
  • USB controller + "custom" logic bus connector (handshake and high data throughput connection to DRAM controller).

Connect them through MicroBlaze PLB 4.6 connection (without "custom" logic bus connector) is also possible but probably slower (in a significant way).