XPS_FX2 is a communication core to interface Xilinx Microblaze soft processor and a popular USB High Speed microcontroller Cypress CY7C68013A (also known as EzUSB FX2).
The XPS_FX2 supports 8bit Slave FIFO mode of operation on FX2 side. The FX2 has 4 endpoints with 2kB buffers (EP2, EP4, EP6, EP8).
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The FX2 firmware was designed to support 4 high speed slave FIFOs: 3x TX (to PC, EP2-4-6), 1x RX (from PC, EP8). The EP2-4-6 are FPGA outputs and EP8 is FPGA input. This asymmetry is a consequence of the core being developed for data streaming to the PC (DAQ boards,cameras…). |
The XPS_FX2 core side is driven by 48MHz IFCLK which is provided by FX2. The other side is driven by PLB clock and two separate clock signals for the data FIFOs.
The FIFOs can be accessed with PLB bus and/or through direct high speed FIFO ports.
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The PLB bus FIFO access is only possible if the PLB clock matches FIFO clock. |
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Maximal supported bandwidth is normally limited by
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(1) Reference design case: Logic Architecture Layer = Reference Architecture Layer and reference USB FX2 μC firmware used
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The XPS_FX2 has 4 interfaces:
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(1) Address FIFO was designed to avoid FIFO draining before the EP ADDRESS changing. Will be fixed in further releases. (2) Set to 1 only if the user experience 8-bit data shifting after a received packet of data. Normally set to 0. |
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The point to point unidirectional buses use simple handshaking protocol.
When (slave) “ready” signal is high the port is open for writing.
A write is performed when “valid” signal goes high. The “data” should be valid when valid signal is high. If “valid” signal goes high and the ready is low then the data are discarded.
The signals are updated on rising edge of clock.
The “valid” signal can be also continuous.
FIFO_IN port is ready when it is not under reset or being full.
If FIFO_OUT port is not ready then it will not send data ("valid" stays low and data stays in FIFO).
FIFO_OUT port latency to act upon "ready" goes low is 1 cycle.
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XPS_FX2 has a full access of a microprocessor to the core functionality through a 5 user 32-bit and 7 IPIF Interrupt registers attached to PLBv4.6 bus.
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The First (LSB) interrupt from user_logic is masked on the left!! |
The parts of the registers (or the whole registers) with a non-capital designation (e.g. wr_fifo_rst) are usually the names of the HDL signals connected to the described register.
The Control Register is used to control basic peripheral functions. All the bit flags are assembled here.
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(1) Endpoint EP8 is read only and is switched automatically when data arrives. To achieve maximal throughput use only one endpoint and prevent TX FIFO draining (TX FIFO empty should not occur). (2) Packet end timeout timer automatically asserts USB_PKTEND signal when TX_FIFO is empty for a programmed number of cycles and current USB EndPoint FIFO is not empty. Cycle timer is also reset when switched to EP8 – incoming data. The USB_PKTEND send current packet and enables the PC to receive packet smaller than 512 bytes. If user setup the timer properly then the packets are automatically send when there is no more data available in the TX_FIFO. |
This register is used to setup thresholds for interrupt triggering when FIFO occupancy reaches set number of words. For RX FIFO the prog_full flag goes high when number of words in a FIFO is higher than threshold. For TX FIFO the prog_empty flag goes high when number of words in a FIFO is lower than threshold.
The tx_fifo_threshold can have 9, 10 or 11 bits according to size of the TX_FIFO. This register is usually accessed using 16-bit writes.
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In the status register the peripheral reports of the current status. The tx_fifo_count can have 9-13 bits according to size of the TX_FIFO. This register is usually accessed using 16-bit reads
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Single beat write to this register puts a single word (4 bytes) to TX FIFO. For proper operation PLB clock frequency should be less or equal to TX_FIFO_Clk.
Single beat read from this register pops one word (4 bytes) from RX FIFO. For proper operation PLB clock frequency should be less or equal to RX_FIFO_Clk.
With INTR_IPIER register the user can enable/disable peripheral interrupt sources. With INTR_IPISR the user can identify interrupt source. Writing a value to INTR_IPISR also clears interrupt.
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The user must make sure that triggered interrupts will be cleared in a consinstent way (single owner); the user (host computer's software) must only clear triggered interrupts. Otherwise the user will trigger "ghost" interrupts which were not triggered by peripheral, but the interrupt controller itself. |
Writing 0x7 to INTR_DIER will enable IP interrupt sources and writing 0x80000000 to INTR_DGIER will enable global interrupt.
The image below presents a conection of user logic interrupt to INTR_IPIER and INTR_IPISR.
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By setting control register (CR) make sure that user not override the previously set bits. |
Resetting the TX_FIFO:
1. Write 0x00000001 to CR
2. Write 0x00000000 to CR
Resetting the RX_FIFO:
1. Write 0x00000002 to CR
2. Write 0x00000000 to CR
Setting the endpoint address to EP4
1. Write 0x00000010 to CR
XPS_NPI_DMA and XPS_FX2 custom IP blocks are both necessary to connect (throgh USB connection) host computer's software and TE USB FX2 module's DRAM.
, , are used for data throughput and integrity test.
MB Commands require the XPS_I2C_SLAVE custom IP block and a proper FX2 interrupt handler (i2c_slave_int_handler() function in interrupt.c running on MicroBlaze); the FX2 interrupt handler is called to handle the signal interrupt xps_i2c_slave_0_IP2INTC_Irpt. The i2c_slave_int_handler() function actually execute the I2C delivered MB Command.
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Write test should be executed before read test; otherwise the read test will fail. |