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Maximal supported bandwidth is normally limited by - FX2 microcontroller's USB connection with host computer (see here);
- FX2 microcontroller's FIFO interface with FPGA; this interface can transfer up to 48 MB/s burst rate.
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| title | FD[7:0] bus pins: FPGA <-> USB FX2 microcontroller connection; |
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Pin Name | FPGA Direction | FX2 direction | Description | In the reference design case (1) |
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| FD[7:0] | Bidirectional | Bidirectional | FD[0:7] are used for byte data transfer
between FPGA and USB FX2 μC. | If the custom IP blocks and MicroBlaze API Commands (MB Commands) are used, data bytes array could be transfered between - TE USB FX2 module's DRAM (MicroBlaze's software) and
- host computer's memory (host computer's software)
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(1) Reference design case: Logic Architecture Layer = Reference Architecture Layer and reference USB FX2 μC firmware used
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| title | System integration block scheme |
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