Page History

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template (note: inner scroll ignore/only only with drawIO object):

      Scroll Title
      anchor Figure_xyz title Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, use Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      
      

    • Table template:

      • Layout macro can be use for landscape of large tables
      • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

    • 
      

      Scroll Title
      anchor Table_xyz title Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

      
      

• ...

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• Vitis/Vivado 2020.2
• PetaLinux
• RF Analyzer 1.6
• PCIe (endpoint)
• SD
• ETH
• USB
• I2C
• RTC
• FMeter
• Modified FSBL for SI5395 programming
• Special FSBL for QSPI programming

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if  issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of hardware which was used to generate the design
• mark the module and carrier board, which was used tested with an ^*

^*used as reference

^*used as reference

^*used as reference

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  • 
    

    Scroll Title
    anchor Table_PF title-alignment center title Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Source *.scr Distro Boot file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

    
    

• Important set new Vivado version link on every Design update of new vivado version!
• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only
  • SI5338 CLKs:
    • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
    • expected CLK Frequ:...
      

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/F_reg[*]/D}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_A_B_DATA_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_ALU_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_OUTPUT_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/toggle_reg/C}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/*/bl.DSP48E_2/DSP_C_DATA_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[4].COUNTER_F_inst/bl.DSP48E_2/DSP_ALU_INST/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[4].COUNTER_F_inst/bl.DSP48E_2/DSP_OUTPUT_INST/*}]
set_false_path -from [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[5].COUNTER_F_inst/bl.DSP48E_2/DSP_ALU_INST/CLK}] -to [get_pins -hier -filter {name=~*labtools_fmeter_0/U0/FMETER_gen[5].COUNTER_F_inst/bl.DSP48E_2/DSP_OUTPUT_INST/*}]

#----------------------------------------------------------------------
# Title      : Example top level constraints for UltraScale+ RF Data Converter
#----------------------------------------------------------------------
# File       : usp_rf_data_converter_0_example_design.xdc
#----------------------------------------------------------------------
# Description: Xilinx Constraint file for the example design for
#              UltraScale+ RF Data Converter core
#---------------------------------------------------------------------
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
# 
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
# 
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES. 
#
#---------------------------------------------------------------------

#------------------------------------------
# TIMING CONSTRAINTS
#------------------------------------------
# Set AXI-Lite Clock to 100MHz
#create_clock -period 10.000 -name usp_rf_data_converter_0_axi_aclk [get_pins axi_aclk_i/CFGMCLK]

# ADC Reference Clock for Tile 0 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc0_clk [get_ports adc0_clk_p]

# ADC Reference Clock for Tile 1 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc1_clk [get_ports adc1_clk_p]

# ADC Reference Clock for Tile 2 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc2_clk [get_ports adc2_clk_p]

# ADC Reference Clock for Tile 3 running at 245.760 MHz
create_clock -period 4.069 -name usp_rf_data_converter_0_adc3_clk [get_ports adc3_clk_p]

# DAC Reference Clock for Tile 0 running at 307.200 MHz
create_clock -period 3.255 -name usp_rf_data_converter_0_dac0_clk [get_ports dac0_clk_p]

# DAC Reference Clock for Tile 1 running at 307.200 MHz
create_clock -period 3.255 -name usp_rf_data_converter_0_dac1_clk [get_ports dac1_clk_p]

set_multicycle_path -to [get_pins -filter {REF_PIN_NAME== D} -of [get_cells -hier -filter {name =~ *usp_rf_data_converter_0_ex_i/ex_design/usp_rf_data_converter_0/inst/IP2Bus_Data_reg*}]] -setup 2
set_multicycle_path -to [get_pins -filter {REF_PIN_NAME== D} -of [get_cells -hier -filter {name =~ *usp_rf_data_converter_0_ex_i/ex_design/usp_rf_data_converter_0/inst/IP2Bus_Data_reg*}]] -hold 1
###############################################################################
# False paths
# For debug in synth use
# report_timing_summary -setup -slack_lesser_than 0
###############################################################################
# Data generator/capture constraints
set rfa_from_list   [get_cells -hier -regexp .*rf(?:da|ad)c_exdes_ctrl_i\/(?:da|ad)c_exdes_cfg_i\/.+num_samples_reg.*]
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_00*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_00*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_01*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_01*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_02*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_02*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_03*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_03*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_10*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_10*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_11*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_11*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_12*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_12*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_13*addrb_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_dac_signal_list [get_cells -hier -filter {name=~*dg_slice_13*addrbend_reg}]
set_false_path -from $rfa_from_list -to $rfa_dac_signal_list
set rfa_from_list   [get_cells -hier -regexp .*rf(?:da|ad)c_exdes_ctrl_i\/(?:da|ad)c_exdes_cfg_i\/.+num_samples_reg.*]
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_00*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_01*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_02*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_03*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_10*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_11*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_12*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_13*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_20*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_21*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_22*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_23*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_30*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_31*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_32*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*addra_reg[*]}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*working_i_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*cap_complete_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list
set rfa_adc_signal_list [get_cells -hier -filter {name=~*ds_slice_33*wea_r_reg}]
set_false_path -from $rfa_from_list -to $rfa_adc_signal_list

• optional chapter separate

• sections for different apps

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2020.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2020.2 xilisf_v5_11

• Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2020.2 FSBL

General:

• Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c (for hooks and board)

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};


/* SDIO */

&sdhci1 {
   disable-wp;
   no-1-8-v;
};

/* ETH PHY */
&gem3 {

	status = "okay";
  ethernet_phy0: ethernet-phy@0 {
		compatible = "marvell,88e1510";
		device_type = "ethernet-phy";
    		reg = <1>;
	};
};
/* USB 2.0 */
 
/* USB  */
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
 	 snps,dis_u2_susphy_quirk;
  	snps,dis_u3_susphy_quirk;
};
   
&usb0 {
    status = "okay";
    /delete-property/ clocks;
    /delete-property/ clock-names;
    clocks = <0x3 0x20>;
    clock-names = "bus_clk";
};




/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

// This I2C Port can be found in the RFSoC Module TE0835 to control PLL chip SI5395A-A-GM on the
// RFSoC Module.

&i2c1 {
  eeprom: eeprom@50 { 
     compatible = "atmel,24c08";
     reg = <0x50>;
  };
};

// This I2C Port connects RFSoC FPGA on the RFSoC Module and I2C multiplexer Chip on the carrier
// board through B2B connector.  

&i2c0 {

	// This I2C multiplexer chip can be found in TEB0835 carrier board.

	i2c_mux@70 { /* TCA9544APWR U7 in the carrier board TEB0835 */
		compatible = "nxp,pca9544";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 { /* FireFly_B*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		i2c@1 { /* FireFly_A*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		i2c@3 { /* LM96163CISD/NOPB U9 FAN Controller in the carrier board TEB0835*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			temp@4c {/* lm96163 - u9*/
			   	compatible = "national,lm96163";
			    	reg = <0x4c>;
			  };
		};
		i2c@4 { /* SI5395A-A-GM U5 DPLL in the carrier board TEB0835*/
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			clock-generator@68{/* SI5395A-A-GM U5 DPLL in the carrier board TEB0835 */
				      	compatible = "silabs,si5395";
				      	reg = <0x68>;
				    	};
		};
	};
};

• Add description for other Software, for example SI CLK Builder ...
• SI5338 and SI5345 also Link to:
  • Si5345
  • Si5338

• Note this list must be only updated, if the document is online on public doc!
• It's semi automatically, so do following
  

  • Add new row below first

  • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports