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| Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
|---|---|---|---|---|---|
| BOOT_R / BOOTMODE_R | out | N12 | NONE | 3.3V | If low than then the QSPI flash can not be written. (Write protect) |
| BOOT_R5 / BOOTMODE_R5 | out | M11 | DOWN | 3.3V | If low than then the QSPI flash will be reset. (HOLD/RESET) |
| CLK_125MHz | in | G13 | NONE | 1.8V | 125MHZ Clock Output of Ethernet transceiver chip (88E1512-A0-NNP2C000) that synchronized with the 25MHZ reference clock |
| EN_3V3 | out | A2 | DOWN | 3.3V | If high than then the 3.3V power will be switched ON. |
| EN1 | in | A9 | UP | 3.3V | User Enable. It is connected in the schematic with B2B connector (JM1-28). The logic of this pin can be changed with DIP Switch on the carrier board. |
| ETH-CLK-EN / EN_ETH_CLK | out | J14 | NONE | 1.8V | Enable pin for U9 oscillator chip U9 (SiT8008BI-73-18S-25.000000E) to feed a clock to Ethernet Transceiver(U8). Enabled as default. |
| ETH-MDC / mdc | in | L14 | UP | 1.8V | Management Data Clock reference for the Ethernet transceiver chip. This pin is connected with MIO52 of FPGA too and can be activated in Zynq7 adjustment. |
| ETH-MDIO / mdio | inout | K14 | UP | 1.8V | It is Management Data pin of Ethernet transceiver chip to transfer in and out of the device synchronously to mdc. It is connected with MIO53 of FPGA. |
| ETH-RST | out | E14 | DOWN | 1.8V | Reset pin of Ethernet transceiver chip. (Active low) |
| INIT | in | C9 | UP | 3.3V | INIT_B_0 pin of FPGA. (Active low). This pin must be tristate for PL configuratuion. By user or device held low until is ready to be configured. |
| INT1 / INT2 | in | P4 | UP | 3.3V | MEMS Interrupt 1 of 3D accelerometer and 3D magnetometer chip U22 (LSM303DTR) (Active High) |
| INT2 / INT1 | in | P6 | UP | 3.3V | MEMS Interrupt 2 of 3D accelerometer and 3D magnetometer chip U22 (LSM303DTR) (Active High) |
| JTAGMODE | in | B9 | 3.3V | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) | |
| LED1 | out | P2 | NONE | 3.3V | Display green LED (D2) |
| LED2 | out | N3 | DOWN | 3.3V | Display red LED (D5) |
| MEM-MAC / MAC_IO | inout | M14 | UP | 1.8V | Serial Clock/Data input/Output of Serial EEPROM (11AA02E48T-I/TT) U17 |
| MEM-SHA / SHA_IO | inout | N14 | UP | 1.8V | SDA for CryptoAuthentication Chip (ATSHA204A-STUCZ-T) U10 |
| MIO14 | inout | M4 | NONE | 3.3V | RX pin of UART0 |
| MIO15 | inout | N4 | NONE | 3.3V | TX pin of UART0 |
| MIO7 | in | P11 | UP | 3.3V | ????? It seems that this pin be used as GPIO. |
| MMC_RST | out | G14 | DOWN | 1.8V | Reset pin of eMMC memory (MTFC16GJVEC-2M WT) U15 |
| MODE / BOOTMODE_IN | in | C8 | UP | 3.3V | This pin is connected with B2B (JM1-32). Latched as BOOTMODE once at power-up, can be used later as I/O, weak pullup |
| MODE / BOOTMODE_IN2 | in | M9 | UP | 3.3V | This pin is connected with B2B (JM1-32). Latched as BOOTMODE once at power-up, can be used later as I/O, weak pullup |
| MR / POR_B | out | P12 | UP | 3.3V | Power-on-reset pin. This pin is connected with supply voltage monitor chip (TPS3106K33DBVR) U26 and controls the PS_POR_B pin of FPGA. (Active Low) |
| NetU19_B12 | B12 | / currently_not_used | |||
| NetU19_B13 | B13 | / currently_not_used | |||
| NetU19_B2 | B2 | / currently_not_used | |||
| NetU19_B3 | B3 | / currently_not_used | |||
| NetU19_B7 | B7 | / currently_not_used | |||
| NetU19_C1 | C1 | / currently_not_used | |||
| NetU19_C10 | C10 | / currently_not_used | |||
| NetU19_C12 / Dummy | out | C12 | DOWN | 3.3V | |
| NetU19_C3 | C3 | / currently_not_used | |||
| NetU19_C6 / RST | in | C6 | UP | 3.3V | |
| NetU19_C7 | C7 | / currently_not_used | |||
| NetU19_E1 | E1 | / currently_not_used | |||
| NetU19_E12 | E12 | / currently_not_used | |||
| NetU19_F13 | F13 | / currently_not_used | |||
| NetU19_F3 | F3 | / currently_not_used | |||
| NetU19_G3 | G3 | / currently_not_used | |||
| NetU19_H3 | H3 | / currently_not_used | |||
| NetU19_J3 | J3 | / currently_not_used | |||
| NetU19_K13 | K13 | / currently_not_used | |||
| NetU19_K3 | K3 | / currently_not_used | |||
| NetU19_L3 | L3 | / currently_not_used | |||
| NetU19_M12 | M12 | / currently_not_used | |||
| NetU19_M2 | M2 | / currently_not_used | |||
| NetU19_M3 | M3 | / currently_not_used | |||
| NetU19_N13 | N13 | / currently_not_used | |||
| NetU19_N5 | N5 | / currently_not_used | |||
| NetU19_N7 | N7 | / currently_not_used | |||
| NetU19_N8 | N8 | / currently_not_used | |||
| NOSEQ | inout | A3 | DOWN | 3.3V | Usage CPLD Variant depends. This pin is connected with B2B NOSEQ pin. |
| ON_1V0 | out | A12 | NONE | 3.3V | Enable pin for 1.0 V DC-DC (Active High) |
| ON_1V5 | out | M7 | NONE | 3.3V | Enable pin for 1.5 V DC-DC (Active High) |
| ON_1V8 | out | A11 | NONE | 3.3V | Enable pin for 1.8 V DC-DC (Active High) |
| OTG-RST | out | B14 | DOWN | 1.8V | Reset pin for high speed USB transceiver (USB3320C-EZK) U18 (Active Low) |
| PG_1V0 | in | A7 | UP | 3.3V | Power OK (POK) pin of 1.0V DC-DC converter EN6347QI (U1). If High then the output voltage of regulator is within 10% of nominal value (OK). |
| PG_1V5 | in | N6 | UP | 3.3V | Power OK (POK) pin of 1.5V DC-DC converter EP53F8QI (U2). If High then the output voltage of regulator is Ok. |
| PG_1V8 | in | A10 | UP | 3.3V | Power OK (POK) pin of 1.8V DC-DC converter EP53F8QI (U3). If High then the output voltage of regulator is Ok. |
| PG_3V3 / POR | in | C11 | UP | 3.3V | |
| PGOOD | inout | B8 | UP | 3.3V | |
| PHY_CONFIG | inout | C14 | DOWN | 1.8V | |
| PHY_LED0 | inout | F14 | NONE | 1.8V | |
| PHY_LED1 | inout | D12 | NONE | 1.8V | |
| PHY_LED2 | inout | C13 | NONE | 1.8V | |
| PJTAG_R | out | N10 | NONE | 3.3V | |
| PROG_B | in | A13 | UP | 3.3V | |
| PS-RST / SRST_B | out | M13 | UP | 1.8V | |
| PUDC_B | inout | E3 | DOWN | VCCIO34 | |
| RESIN | in | C4 | UP | 3.3V | |
| RST / RST_SENSE | in | P3 | NONE | 3.3V | |
| RTC_INT | in | N2 | UP | 3.3V | |
| SCL | inout | P8 | UP | 3.3V | |
| SDA | inout | P7 | UP | 3.3V | |
| SPK_L | M5 | / currently_not_used | |||
| SPK_R | M8 | / currently_not_used | |||
| TCK / C_TCK | out | P13 | DOWN | 3.3V | |
| TDI / C_TDI | out | P9 | DOWN | 3.3V | |
| TDO / C_TDO | in | M10 | DOWN | 3.3V | |
| TMS / C_TMS | out | N9 | DOWN | 3.3V | |
| VCCIO34 | E2 | / currently_not_used | |||
| VCCIO34 | F2 | / currently_not_used | |||
| VCCIO34 | H2 | / currently_not_used | |||
| VCCIO34 | J2 | / currently_not_used | |||
| VCCIO34 | K2 | / currently_not_used | |||
| X_TCK / M_TCK | in | B6 | DOWN | 3.3V | |
| X_TDI / M_TDI | in | B4 | DOWN | 3.3V | |
| X_TDO / M_TDO | out | A4 | DOWN | 3.3V | |
| X_TMS / M_TMS | in | A6 | DOWN | 3.3V | |
| X1 | in | F1 | UP | VCCIO34 | |
| X2 / XIO4 | inout | C2 | UP | VCCIO34 | |
| X3 / XIO5 | inout | B1 | UP | VCCIO34 | |
| X4 / XIO6 | inout | D1 | UP | VCCIO34 | |
| X5 | out | J1 | NONE | VCCIO34 | |
| X6 | H1 | / currently_not_used | |||
| X7 | in | M1 | UP | VCCIO34 | |
| XCLK | out | K1 | NONE | VCCIO34 | |
| - / SIG1 | in | E13 | NONE | 1.8V | This port exists in VHDL code but this pin is connected with 1.8V in the schematic REV03 ???? |
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