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Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/DownBank PowerDescription
BOOT_R / BOOTMODE_RoutN12NONE3.3VIf low then the QSPI flash can not be written. (Write protect)
BOOT_R5 / BOOTMODE_R5outM11DOWN3.3VIf low then the QSPI flash will be reset. (HOLD/RESET)
CLK_125MHzinG13NONE1.8V125MHZ Clock Output of Ethernet transceiver chip (88E1512-A0-NNP2C000) that synchronized with the 25MHZ reference clock
EN_3V3outA2DOWN3.3VIf high then the 3.3V power will be switched ON.
EN1inA9UP3.3VUser Enable. Enables the DC-DC converters and on board supplies (Active High). (B2B JM1-28)(DIP Switch on the carrier board) . Not used if NOSEQ = '1'
ETH-CLK-EN / EN_ETH_CLKoutJ14NONE1.8VEnable pin for U9 oscillator chip U9 (SiT8008BI-73-18S-25.000000E) to feed a clock to Ethernet Transceiver(U8). Enabled as default.
ETH-MDC / mdcinL14UP1.8VManagement Data Clock reference for the Ethernet transceiver chip. This pin is connected with MIO52 of FPGA too and can be activated in Zynq7 adjustment.
ETH-MDIO / mdioinoutK14UP1.8VIt is Management Data pin of Ethernet transceiver chip to transfer in and out of the device synchronously to mdc. It is connected with MIO53 of FPGA.
ETH-RSToutE14DOWN1.8VReset pin of Ethernet transceiver chip. (Active low)
INITinC9UP3.3VINIT_B_0 pin of FPGA. (Active low). This pin must be tristate for PL configuratuion. By user or device held low until is ready to be configured.
INT1 / INT2inP4UP3.3VMEMS Interrupt 1 of 3D accelerometer and 3D magnetometer chip U22 (LSM303DTR) (Active High)
INT2 / INT1inP6UP3.3VMEMS Interrupt 2 of 3D accelerometer and 3D magnetometer chip U22 (LSM303DTR) (Active High)
JTAGMODEinB9
3.3VEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
LED1outP2NONE3.3VDisplay green LED (D2)
LED2outN3DOWN3.3VDisplay red LED (D5)
MEM-MAC / MAC_IOinoutM14UP1.8VSerial Clock/Data input/Output of Serial EEPROM (11AA02E48T-I/TT) U17
MEM-SHA / SHA_IOinoutN14UP1.8VSDA for CryptoAuthentication Chip (ATSHA204A-STUCZ-T) U10
MIO14inoutM4NONE3.3VRX pin of UART0
MIO15inoutN4NONE3.3VTX pin of UART0
MIO7inP11UP3.3VThis pin is used as GPIO.
MMC_RSToutG14DOWN1.8VReset pin of eMMC memory (MTFC16GJVEC-2M WT) U15
MODE / BOOTMODE_INinC8UP3.3VLatched as BOOTMODE once at power-up, can be used later as I/O, weak pull up. Force low for boot from the SD Card. Latched at power on only, not on soft reset (B2B-JM1 pin 32) 
MODE / BOOTMODE_IN2inM9UP3.3VLatched as BOOTMODE once at power-up, can be used later as I/O, weak pull up. Force low for boot from the SD Card. Latched at power on only, not on soft reset (B2B-JM1 pin 32) 
MR     / POR_BoutP12UP3.3VPower-on-reset pin. This pin is connected with supply voltage monitor chip (TPS3106K33DBVR) U26 and controls the PS_POR_B pin of FPGA. (Active Low)
NetU19_B12
B12

/ currently_not_used
NetU19_B13
B13

/ currently_not_used
NetU19_B2
B2

/ currently_not_used
NetU19_B3
B3

/ currently_not_used
NetU19_B7
B7

/ currently_not_used
NetU19_C1
C1

/ currently_not_used
NetU19_C10
C10

/ currently_not_used
NetU19_C12 / DummyoutC12DOWN3.3V
NetU19_C3
C3

/ currently_not_used
NetU19_C6 / RSTinC6UP3.3V
NetU19_C7
C7

/ currently_not_used
NetU19_E1
E1

/ currently_not_used
NetU19_E12
E12

/ currently_not_used
NetU19_F13
F13

/ currently_not_used
NetU19_F3
F3

/ currently_not_used
NetU19_G3
G3

/ currently_not_used
NetU19_H3
H3

/ currently_not_used
NetU19_J3
J3

/ currently_not_used
NetU19_K13
K13

/ currently_not_used
NetU19_K3
K3

/ currently_not_used
NetU19_L3
L3

/ currently_not_used
NetU19_M12
M12

/ currently_not_used
NetU19_M2
M2

/ currently_not_used
NetU19_M3
M3

/ currently_not_used
NetU19_N13
N13

/ currently_not_used
NetU19_N5
N5

/ currently_not_used
NetU19_N7
N7

/ currently_not_used
NetU19_N8
N8

/ currently_not_used
NOSEQinoutA3DOWN3.3VUsage CPLD Variant depends. (B2B-NOSEQ pin 7) Forces the 1.0V and 1.8V DC-DC converters always ON when high. Can be used as an I/O after boot.
ON_1V0outA12NONE3.3VEnable pin for 1.0 V DC-DC (Active High)
ON_1V5outM7NONE3.3VEnable pin for 1.5 V DC-DC (Active High)
ON_1V8outA11NONE3.3VEnable pin for 1.8 V DC-DC (Active High)
OTG-RSToutB14DOWN1.8VReset pin for high speed USB transceiver (USB3320C-EZK) U18 (Active Low)
PG_1V0inA7UP3.3VPower OK (POK) pin of 1.0V DC-DC converter EN6347QI (U1). If High then the output voltage of regulator is within 10% of nominal value (OK).
PG_1V5inN6UP3.3VPower OK (POK) pin of 1.5V DC-DC converter EP53F8QI (U2). If High then the output voltage of regulator is Ok.
PG_1V8inA10UP3.3VPower OK (POK) pin of 1.8V DC-DC converter EP53F8QI (U3). If High then the output voltage of regulator is Ok.
PG_3V3 / PORinC11UP3.3VPOR Reset pin. This pin is connected with PG_3V3. As long as the VCCIO34 voltage is zero, this pin will remain low.
PGOODinoutB8UP3.3VPower good output as default, can be used as I/O. (B2B JM1-Pin 30) Forced low until all on-board power supplies are working properly.
PHY_CONFIGinoutC14DOWN1.8VHardware configuration pin of Ethernet transceiver (88E1512-A0-NNP2C000).
PHY_LED0inoutF14NONE1.8VLED output 0 of Ehternet transceiver chip
PHY_LED1inoutD12NONE1.8VLED output 1 of Ehternet transceiver chip
PHY_LED2inoutC13NONE1.8VLED output 2 or interrupt output pin (Active Low) of Ehternet transceiver chip
PJTAG_RoutN10NONE3.3VThis pin in the schematic is connected with SPI-DQ0/M0 Pin
PROG_BinA13UP3.3V

By pulsing this pin any configuration that is currently loaded is cleared and the PL prepared to load new configuration. (Active Low)

PS-RST / SRST_BoutM13UP1.8VPS software reset  (Active Low)
PUDC_BinoutE3DOWNVCCIO34

Selects the enable or disable of pull-ups during configuration on the user I/O pins. (Active Low)  Enables internal pull-up resistors on the

select I/O pins after power-up and during configuration.

RESINinC4UP3.3VMaster reset input (Active Low). Default mapping forces POR_B reset to Zynq PS
RST / RST_SENSEinP3NONE3.3VReset pin that is connected with PS_PORT_B (Power-on-reset) (Active Low)
RTC_INTinN2UP3.3VInterrupt output or frequency output of RTC chip (ISL12020MIRZ) U20 (Active Low)
SCLinoutP8UP3.3VI2C clock pin of MEMS chip (LSM303DTR) U22
SDAinoutP7UP3.3VI2C data pin of MEMS chip (LSM303DTR) U22
SPK_L
M5

/ currently_not_used
SPK_R
M8

/ currently_not_used
TCK / C_TCKoutP13DOWN3.3VZynq JTAG clock pin
TDI / C_TDIoutP9DOWN3.3VZynq JTAG data input pin
TDO / C_TDOinM10DOWN3.3VZynq JTAG data output pin
TMS / C_TMSoutN9DOWN3.3VZynq JTAG mode select pin
VCCIO34
E2

/ currently_not_used
VCCIO34
F2

/ currently_not_used
VCCIO34
H2

/ currently_not_used
VCCIO34
J2

/ currently_not_used
VCCIO34
K2

/ currently_not_used
X_TCK / M_TCKinB6DOWN3.3VFTDI JTAG clock pin (B2B-JM1-pin 99)
X_TDI / M_TDIinB4DOWN3.3VFTDI JTAG data input pin (B2B-JM1-pin 95)
X_TDO / M_TDOoutA4DOWN3.3VFTDI JTAG data output pin (B2B-JM1-pin 97)
X_TMS / M_TMSinA6DOWN3.3VFTDI JTAG mode select pin (B2B-JM1-pin 93)
X1inF1UPVCCIO34CPLD pin to the FPGA (L16). I2C clock from FPGA
X2 / XIO4inoutC2UP

VCCIO34

CPLD pin to the FPGA (M15). ETH PHY LED0
X3 / XIO5inoutB1UPVCCIO34CPLD pin to the FPGA (N15). ETH PHY LED1
X4 / XIO6inoutD1UPVCCIO34CPLD pin to the FPGA (P16). ETH PHY LED2
X5outJ1NONEVCCIO34CPLD pin to the FPGA (P22). I2C data to FPGA
X6
H1

/ currently_not_used
X7inM1UPVCCIO34CPLD pin to the FPGA (N22). I2C data from FPGA
XCLKoutK1NONEVCCIO34CPLD pin to the FPGA (K19). ETH PHY clock to FPGA
- / SIG1inE13NONE1.8VThis pin is connected with VCCIO34 directly in the schematic REV03 and has no lable in the schematic.

SC B2B Pins

NameB2BModeDefault functionAlternativeDescription
EN1JM1-Pin 28input, weak pull-upPower EnableIOHigh enables the DC-DC converters and on-board supplies. Not used if NOSEQ=1
MODEJM1-Pin 32input, weak pull-upBoot modeSDA or IOForce low for boot from the SD Card. Latched at power on only, not on soft reset!
NOSEQJM1-Pin 7input, weak pull-downPower sequencing ControlOutputForces the 1.0V and 1.8V DC-DC converters always ON when high. Can be used as an I/O after boot.
PGOODJM1-Pin 30output, open drainPower goodSCL or IOForced low until all on-board power supplies are working properly.
Attention: During CPLD programming, this pins is high impedance.
RESINJM2-Pin 18input, weak pull-upReset inputIOActive Low Reset input, default mapping forces POR_B reset to Zynq PS

...

Schematic net nameDefault functionDirectionSC pinFPGA pinDescription
XCLKETH PHY Clock to FPGAto FPGAK1K19
X7I2C Data from FPGAfrom FPGAM1N22SDA from EMIO I2Cx
X5I2C Data to FPGAto FPGAJ1P22SDA to EMIO I2Cx
X4ETH PHY LED2to FPGAD1P16
X3ETH PHY LED1to FPGAB1N15RTC, MEMS Interrupt or PHY LED1
X2ETH PHY LED0to FPGAC2M15
X1I2C Clock from FPGAfrom FPGAF1L16SCL from EMIO I2Cx
PUDCEnables internal pull-up resistors on the IOsto FPGAE3K16normally not used tied to fixed level by SC


SC registers

NOSEQ,  LED1 and LED2 functions can be changed from the default behaviour using output port bits CR1[11:8], CR1[3:0] and CR1[7:4].

Most registers and functions are available via ETH PHY Management interface (MIO pins 52 and 53).

AddrR/WRegister nameDescripion
0RO

1RO

2ROID1PHY Identifier Register 1
3ROID2PHY Identifier Register 2
4RW?Auto-Negotiation advertisement register
5RWCR1Control Register 1: LED's
6RWCR2Control Register 2; XIO Control
7RWCR3Control Register 3; Reset, Interrupt
8ROSR1Status Register
9ROMAChiHighest bytes of primary MAC Address
0xAROMACmiMiddle bytes of primary MAC Address
0xBROMACloLowest bytes of primary MAC Address
0xCROCR4reserved do not use
0xDRWMMD_CRMMD Control Register
0xERWMMD_ADMMD Address/Data
0xF-
reserved do no use
other-
reserved do not use


NOSEQ Signal

Value (CR1[11:8])NOSEQ
0001PHY_LED0
0010PHY_LED1
0011PHY_LED2
0100MIO7
0101RTC_INT
0110OFF
0111ON
1000XIO6
1001uio_unidir
1010Undefined
Value (CR1[3:0])LED1 (Green)Value (CR1[7:4])LED2 (Red)Value (CR1[11:8])NOSEQDescription0001

PHY_LED0

0001PHY_LED00001PHY_LED00010

PHY_LED1

0010PHY_LED10010PHY_LED10011

PHY_LED2

0011PHY_LED20011PHY_LED20100

MIO7

0100MIO70100MIO70101

RTC_INT

0101RTC_INT0101RTC_INT0110

OFF

0110OFF0110OFF0111

ON

0111ON0111ON1000XIO41000XIO51000XIO61001Not MIO141001Not MIO151001uio_unidir1010Not MIO14/Not MIO151010Not MIO14/Not MIO151010UndefinedDefaultMIO7Defaultmodeblink
DefaultPHY_LED0


Register CR1

CR1Description
15:12-
11:8NOSEQ Mux
7:4LED1 Mux
3:0LED2 Mux

The mapping of CPLD IOs that are connected directly with FPGA, can be changed using output port bits CR2[11:0].  


Register CR2

CR2Description
15:12XCLK Mux
11:8XIO6 Mux
7:4XIO5 Mux
3:0XIO4 Mux


Register CR3

CR3 bitrelated functionSignal
0MEMS interrupt 1INT1
1MEMS interrupt 2INT2
2Real time clock interruptRTC_RST
3Interrupt output pin of ethernet transceiverPHY_LED2
4Reset for high speed USB transceiverOTG_RST
5Reset for ethernet transceiver / Reset for serial for  unio mac read coreETH_RST
6Reset for MMCMMC_RST
7Enable for ETH clockEN_ETH_CLK
15:8Enable for watch dog timer / Extra enable

if 0xE5 -→ WDT enable

if 0xA5 -→ Extra enable


The mapping of CPLD IOs (XIO4,XIO5,XIO6 and XCLK) that are connected directly with FPGA, can be changed using output port bits CR2.  

Signal XIO4

Value (CR2[3:0])XIO4
0001

MIO7

0010

SHA_IO

0011MAC_IO
1000uio_unidir
0110'Z'
Value (CR2[3:0])XIO4Value (CR2[7:4])XIO5Value (CR2[11:8])XIO6Value (CR2[15:12])XCLKDescription0001

MIO7

0001

MIO14

0001

MIO15

0001RTC_INT0010

SHA_IO

0010Undefined0010Undefined0010osc_clk0011MAC_IO0011RTC_INT0011osc_clk0011Undefined1000uio_unidir1000uio_unidir1000uio_unidir1000Undefined0110'Z'0110'Z'0110'Z'0110Undefined0111UndefinedUndefinedUndefined0111INTR
0111Undefined
DefaultPHY_LED0


Signal XIO5

Value
DefaultPHY_LED1DefaultPHY_LED2DefaultCLK_125MHZValue
(CR2[7:4])XIO5
0001

MIO14

0010Undefined
0011RTC_INT
1000uio_unidir
0110'Z'
UndefinedUndefined
DefaultPHY_LED1


Signal XIO6

Value (CR2[11:8])XIO6
0001

MIO15

Description
0010Undefined
1001
0011
XIO5
osc_
in
clk
1001
1000
XIO6
uio_
inXIO5_in and XIO6_in are equal to XIO5 and XIO6 respectively if VCCIO34 voltage equal to 1.8V.else
unidir
0110
'Z'
0111
else
INTR
'Z'
DefaultPHY_LED2


Signal XCLK

Value (CR2[
CR2Description
15:12])XCLK
Mux
11:8XIO6 Mux7:4XIO5 Mux3:0XIO4 Mux

Status register bits mapping:

0001RTC_INT
0010osc_clk
0011Undefined
1000Undefined
0110Undefined
0111Undefined
DefaultCLK_125MHZ


Signal SHA_IO

Value XIO4[3:0]Value XIO5SHA_IO
"0010"'0''0'
else'Z'


Signal MAC_IO

Value XIO4[3:0] MAC_IO
"0011"'0'
elseConnected to internal MAC read block


Signals MIO14 and MIO15

Value (CR2[7:4])MIO14Value (CR2[11:8])MIO15Description
1001XIO5_in1001XIO6_inXIO5_in and XIO6_in are equal to XIO5 and XIO6 respectively if VCCIO34 voltage equal to 1.8V.
else'Z'else'Z'


Status register bits mapping:

SR1Description
0

INT1

1INT2
2RTC_INT
3PHY_LED2
7BOOTMODE_LATCHED
8BOOTMODE_IN2
9BOOTMODE_IN
10NOSEQ
11NOSEQ_LATCHED
12WD_EVENT
13PG_1V5
14EXTRA_ENABLED or WDOG_ENABLED
15mac_valid


The subsystem I2C to GPIO port mapping is according the following table:

I2C to GPIOPin nameCPLD PinDirectionFPGA PinDescription
sda_in (SDA)X7M1from FPGAN22
sda_outX5J1to FPGAP22X5 is sda_in and gpio_sda_out
sclk (SCL)X1F1from FPGAL16
GPIO_input


GPIO_input bitConnected to:
0

PHY_LED0

1PHY_LED1
2MIO7
3NOSEQ
4RESIN_g
5EN1_g
6BOOTMODE_LATCHED
7BOOTMODE_IN
8INT1
9INT2
10RTC_INT
11PHY_LED2
12'0'
13'0'


GPIO_outputNot used


SR1Description0

INT1

1INT22RTC_INT3PHY_LED27BOOTMODE_LATCHED8BOOTMODE_IN29BOOTMODE_IN10NOSEQ11NOSEQ_LATCHED12WD_EVENT13PG_1V514EXTRA_ENABLED or WDOG_ENABLED15mac_validI2C to GPIOPin nameCPLD PinDirectionFPGA PinDescriptionsda_in (SDA)X7M1from FPGAN22sda_outX5J1to FPGAP22X5 is sda_in and gpio_sda_outsclk (SCL)X1F1from FPGAL16GPIO_input
bitDescription
0

PHY_LED0

1PHY_LED1
2MIO7
3NOSEQ
4RESIN_g
5EN1_g
6BOOTMODE_LATCHED
7BOOTMODE_IN
8INT1
9INT2
10RTC_INT
11PHY_LED2
12'0'
13'0'
GPIO_outputNot usedAddrR/WRegister nameDescripion0RO1RO2ROID1PHY Identifier Register 13ROID2PHY Identifier Register 24RW?Auto-Negotiation advertisement register5RWCR1Control Register 1: LED's6RWCR2Control Register 2; XIO Control7RWCR3Control Register 3; Reset, Interrupt8ROSR1Status Register9ROMAChiHighest bytes of primary MAC Address0xAROMACmiMiddle bytes of primary MAC Address0xBROMACloLowest bytes of primary MAC Address0xCROCR4reserved do not use0xDRWMMD_CRMMD Control Register0xERWMMD_ADMMD Address/Data0xF-reserved do no useother-reserved do not use
Value (uio_sm_cnt[8:5])uio_io_dataDescription
0000

MIO7

0001RTC_INT
0010INT1
0100INT2
0011PHY_LED0
0100PHY_LED1
0101PHY_LED2
0110BOOTMODE_IN
0111MIO14
1000MIO15
1001XIO4
1010XIO5
1011XIO6
1100WD_HIT
1101'0'
1110'0'

...

Value (uio_sm_cnt[2:1])uio_unidirDescription
01'0'
10

uio_io_data / uio_id_data

If uio_sm_cnt(4) Low --→  uio_id_data
LED1(Green)ConditionDescription
WD_counter(7)WDOG_ENABLED = '1'
ONPOR_B_i = '0'POR_B_i is '0' if one of the following signals is '0' --->   EN1 or RESIN or PG_ALL or PORDONE
led1outelse
Value (CR1[3:0])Connected to
0001

PHY_LED0

0010

PHY_LED1

0011

PHY_LED2

0100

MIO7

0101

RTC_INT

0110

OFF

0111

ON

1000XIO4
1001Not MIO14
1010Not MIO14/Not MIO15
DefaultMIO7
LED2(Red)ConditionDescriptionpowerblinkEN1_g = '0'EN1_g is delayed EN1.ONPOR_B_i = '0'led2outelseValue (CR1[7:4])Connected to


On-board LEDs

There are 3 on-board LEDs, with two of them connected to the System Management Controller and one to the Zynq PL (Done pin).


NameColorConnected to:Default mapping:
LED1GreenSCPL MIO[7]
LED2RedSCmodeblink
LED3GreenZynq PLFPGA Done - active low

LED1 Green

This LED is mapped to MIO7 after power up. After the Zynq PS has booted it can change the mapping of this LED. If SC can not enable power to the Zynq then this LED will remain under SC control. It is available to the user only after the power supplies have stabilized and the POR reset to the Zynq is released. If watch dog timer is activated this LED will be assigned to the 7th bit of the counter of watch dog timer.

Value (CR1[3:0])LED1 (Green)
0001

PHY_LED0

0010

PHY_LED1

0011

PHY_LED2

0100

MIO7

0101

RTC_INT

0110

OFF

0111

ON

1000
XIO5
XIO4
1001Not
MIO15
MIO14
1010Not MIO14/Not MIO15
Default
modeblink
MIO7


if 0xE5 -→ WDT enable

if 0xA5 -→ Extra enable
LED1(Green)ConditionCR3 bitrelated functionDescription
0MEMS interrupt 1 INT1
1MEMS interrupt 2INT2
2Real time clock interruptRTC_RST
3Interrupt output pin of ethernet transceiverPHY_LED2
4Reset for high speed USB transceiverOTG_RST
5Reset for ethernet transceiver / Reset for serial for  unio mac read coreETH_RST
6Reset for MMCMMC_RST
7Enable for ETH clockEN_ETH_CLK
15:8Enable for watch dog timer / Extra enable
WD_counter(7)WDOG_ENABLED = '1'
ONPOR_B_i = '0'POR_B_i is '0' if one of the following signals is '0' --->   EN1 or RESIN or PG_ALL or PORDONE
led1outelse


Value (CR1[3:0])Connected to:
0001

PHY_LED0

0010

PHY_LED1

0011

PHY_LED2

0100

MIO7

0101

RTC_INT

0110

OFF

0111

ON

1000XIO4
1001Not MIO14
1010Not MIO14/Not MIO15
DefaultMIO7



LED2 Red

This LED is used to show various signal or port states. The function of this LED can be changed by CR1 register.

Value (CR1[7:4])LED2 (Red)
0001PHY_LED0
0010PHY_LED1
0011PHY_LED2
0100MIO7
0101RTC_INT
0110OFF
0111ON
1000XIO5
1001Not MIO15
1010Not MIO14/Not MIO15
Defaultmodeblink


LED2(Red)ConditionDescription
powerblinkEN1_g = '0'EN1_g is delayed EN1.
ONPOR_B_i = '0'
led2outelse


Value (CR1[7:4])Connected to:
0001PHY_LED0
0010PHY_LED1
0011PHY_LED2
0100MIO7
0101RTC_INT
0110OFF
0111ON
1000XIO5
1001Not MIO15
1010Not MIO14/Not MIO15
Defaultmodeblink



LED3 Green (FPGA Done)

This green LED is connected to the FPGA Done pin which has an active low state. As soon as the Zynq is powered and the 3.3V I/O voltage is enabled, this LED will illuminate. This indicates that the Zynq PL is not configured. Once the Zynq PL has been configured the LED will go off.

During normal operation when the Zynq PL has been configured, the LED can be controlled from the FPGA fabric. Control of the LED in a user design requires the use of Xilinx startup primitive rather than a normal I/O primitive. If the startup primitive is not used then the LED will go off after configuration and remain off irrespectively of the user design. This LED can not be controlled by the SC.


Functional Description

JTAG

...