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NOSEQ can be used as an output after boot. NOSEQ must be low when 3.3V power is applied to the module. Common usage is an LED connected between NOSEQ and GND. The mapping of NOSEQ pin can be changed by CR1 register. The CR1 register is control register of MDIO slave interface that its content can be changed with FSBL code on the FPGA.
| Value (CR1[11:8]) | NOSEQ |
|---|---|
| 0001 | PHY_LED0 |
| 0010 | PHY_LED1 |
| 0011 | PHY_LED2 |
| 0100 | MIO7 |
| 0101 | RTC_INT |
| 0110 | OFF |
| 0111 | ON |
| 1000 | XIO6 |
| 1001 | uio_unidir |
| 1010 | Undefined |
| Default | PHY_LED0 |
SC Pins to the FPGA
| Schematic net name | VHDL Name | Default function | Direction | SC pin | FPGA pin | Description |
|---|---|---|---|---|---|---|
| XCLK | XCLK | ETH PHY Clock to FPGA | to FPGA | K1 | K19 | |
| X7 | X7 | I2C Data from FPGA | from FPGA | M1 | N22 | SDA from EMIO I2Cx |
| X5 | X5 | I2C Data to FPGA | to FPGA | J1 | P22 | SDA to EMIO I2Cx |
| X4 | XIO6 | ETH PHY LED2 | to FPGA | D1 | P16 | |
| X3 | XIO5 | ETH PHY LED1 | to FPGA | B1 | N15 | RTC, MEMS Interrupt or PHY LED1 |
| X2 | XIO4 | ETH PHY LED0 | to FPGA | C2 | M15 | |
| X1 | X1 | I2C Clock from FPGA | from FPGA | F1 | L16 | SCL from EMIO I2Cx |
| PUDC_B | PUDC_B | Enables internal pull-up resistors on the IOs | to FPGA | E3 | K16 | normally not used tied to fixed level by SC |
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The mapping of CPLD IOs (XIO4,XIO5,XIO6 and XCLK) that are connected directly with FPGA, can be changed using output port bits CR2 register.
Signal XIO4
| Value (CR2[3:0]) | XIO4 |
|---|---|
| 0001 | MIO7 |
| 0010 | SHA_IO |
| 0011 | MAC_IO |
| 1000 | uio_unidir |
| 0110 | 'Z' |
| 0111 | Undefined |
| Default | PHY_LED0 |
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| Value (CR2[7:4]) | XIO5 |
|---|---|
| 0001 | MIO14 |
| 0010 | Undefined |
| 0011 | RTC_INT |
| 1000 | uio_unidir |
| 0110 | 'Z' |
| Undefined0111 | Undefined |
| Default | PHY_LED1 |
Signal XIO6
| Value (CR2[11:8]) | XIO6 | Description |
|---|---|---|
| 0001 | MIO15 | |
| 0010 | Undefined | |
| 0011 | osc_clk | |
| 1000 | uio_unidir | |
| 0110 | 'Z' | |
| 0111 | INTR | INTR signal can be depending on CR3 register value one of the following interrupt signals: INT1, INT2, RTC_INT, PHY_LED2 |
| Default | PHY_LED2 |
Signal XCLK
| Value (CR2[15:12]) | XCLK | Description |
|---|---|---|
| 0001 | RTC_INT | |
| 0010 | osc_clk | This pin is directly connected to on-chip oscillator signal. (24.18MHZ) |
| 0011 | Undefined | |
| 1000 | Undefined | |
| 0110 | Undefined | |
| 0111 | Undefined | |
| Default | CLK_125MHZ | This pin is connected to output clock pin of ethernet transceiver chip. |
Signal SHA_IO
| Value XIO4[3:0] | Value XIO5 | SHA_IO | |
|---|---|---|---|
| 0010 | "'0' | '0' | |
| else | 'Z' | ||
Signal MAC_IO
| Value XIO4[3:0] | MAC_IO |
|---|---|
| "0011" | '0' |
| else | Connected to internal MAC read block |
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Status register bits mapping:
| SR1 | Description |
|---|---|
| 0 | INT1 |
| 1 | INT2 |
| 2 | RTC_INT |
| 3 | PHY_LED2 |
| 7 | BOOTMODE_LATCHED |
| 8 | BOOTMODE_IN2 |
| 9 | BOOTMODE_IN |
| 10 | NOSEQ |
| 11 | NOSEQ_LATCHED |
| 12 | WD_EVENT |
| 13 | PG_1V5 |
| 14 | EXTRA_ENABLED or WDOG_ENABLED |
| 15 | mac_valid |
The subsystem I2C to GPIO port mapping is according the following table:
| I2C to GPIO | Pin name | CPLD Pin | Direction | FPGA Pin | Description |
|---|---|---|---|---|---|
| sda_in (SDA) | X7 | M1 | from FPGA | N22 | |
| sda_out | X5 | J1 | to FPGA | P22X5 is sda_in and gpio_sda_out | If X7 is High. If X7 is Low, this pin will be disconnected. |
| sclk (SCL) | X1 | F1 | from FPGA | L16 | |
| GPIO_input | Mapping the GPIO_input bits to various ports or signals | ||||
| GPIO_output | Not used | ||||
| GPIO_input bit | Connected to: |
|---|---|
| 0 | PHY_LED0 |
| 1 | PHY_LED1 |
| 2 | MIO7 |
| 3 | NOSEQ |
| 4 | RESIN_g |
| 5 | EN1_g |
| 6 | BOOTMODE_LATCHED |
| 7 | BOOTMODE_IN |
| 8 | INT1 |
| 9 | INT2 |
| 10 | RTC_INT |
| 11 | PHY_LED2 |
| 12 | '0' |
| 13 | '0' |
| Not used | Value (uio_sm_cnt[8:5]) | uio_io_data | ||||
|---|---|---|---|---|---|---|
| 0000 | MIO7 | |||||
| 0001 | RTC_INT | |||||
| 0010 | INT1 | |||||
| 0100 | INT2 | |||||
| 0011 | PHY_LED0 | |||||
| 0100 | PHY_LED1 | |||||
| 0101 | PHY_LED2 | |||||
| 0110 | BOOTMODE_IN | |||||
| 0111 | MIO14 | |||||
| 1000 | MIO15 | |||||
| 1001 | XIO4 | |||||
| 1010 | XIO5 | |||||
| 1011 | XIO6 | |||||
| 1100 | WD_HIT | |||||
| 1101 | '0' | |||||
| 1110 | '0' | |||||
| Value (uio_sm_cnt[2:1]) | uio_unidir | Description |
|---|---|---|
| 01 | '0' | |
| 10 | uio_io_data / uio_id_data | If uio_sm_cnt(4) Low --→ uio_id_data |
On-board LEDs
There are 3 on-board LEDs, with two of them connected to the System Management Controller and one to the Zynq PL (Done pin).
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| LED1(Green) | Condition | Description | |
|---|---|---|---|
| WD_counter(7) | WDOG_ENABLED = '1' | ||
| ON | POR_B_i = '0' | POR_B_i is '0' if one of the following signals is '0' ---> EN1 or RESIN or PG_ALL or PORDONE | |
| led1outVariable | else | Value ( Mapping depending on the CR1[3:0] ) | Connected to: |
| 0001 | PHY_LED0 | ||
| 0010 | PHY_LED1 | ||
| 0011 | PHY_LED2 | ||
| 0100 | MIO7 | ||
| 0101 | RTC_INT | ||
| 0110 | OFF | ||
| 0111 | ON | ||
| 1000 | XIO4 | ||
| 1001 | Not MIO14 | ||
| 1010 | Not MIO14/Not MIO15 | ||
| Default | MIO7 |
LED2 LED2 Red
This LED is used to show various signal or port states. The function of this LED can be changed by CR1 register.
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| LED2(Red) | Condition | Description | |
|---|---|---|---|
| powerblink | EN1_g = '0' | EN1_g is delayed EN1. | |
| ON | POR_B_i = '0' | ||
| led2outVariable | else | Value ( Mapping depending on the CR1[7:4] ) | Connected to: |
| 0001 | PHY_LED0 | ||
| 0010 | PHY_LED1 | ||
| 0011 | PHY_LED2 | ||
| 0100 | MIO7 | ||
| 0101 | RTC_INT | ||
| 0110 | OFF | ||
| 0111 | ON | ||
| 1000 | XIO5 | ||
| 1001 | Not MIO15 | ||
| 1010 | Not MIO14/Not MIO15 | Default | modeblink
LED3 Green (FPGA Done)
This green LED is connected to the FPGA Done pin which has an active low state. As soon as the Zynq is powered and the 3.3V I/O voltage is enabled, this LED will illuminate. This indicates that the Zynq PL is not configured. Once the Zynq PL has been configured the LED will go off.
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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGENB pin of CPLD (B9) (logical one for CPLD, logical zero for FPGA). This pin is connected to B2B (JM1-pin 89) directly. On the carrier board can be this pin enabled or disabled with a dip switch.
| CPLD JTAGENB (B2B JM1-89) | Description |
|---|---|
| 0 | FPGA access |
| 1 | CPLD access |
Power
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Appx. A: Change History and Legal Notices
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Overview
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