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Most registers and functions are available via ETH PHY Management interface (MIO pins 52 and 53).
| Addr | R/W | Register name | Descripion |
|---|---|---|---|
| 0 | RO | ||
| 1 | RO | ||
| 2 | RO | ID1 | PHY Identifier Register 1 |
| 3 | RO | ID2 | PHY Identifier Register 2 |
| 4 | RW | ? | Auto-Negotiation advertisement register |
| 5 | RW | CR1 | Control Register 1: LED's |
| 6 | RW | CR2 | Control Register 2; XIO Control |
| 7 | RW | CR3 | Control Register 3; Reset, Interrupt |
| 8 | RO | SR1 | Status Register |
| 9 | RO | MAChi | Highest bytes of primary MAC Address |
| 0xA | RO | MACmi | Middle bytes of primary MAC Address |
| 0xB | RO | MAClo | Lowest bytes of primary MAC Address |
| 0xC | RO | CR4 | reserved do not use |
| 0xD | RW | MMD_CR | MMD Control Register |
| 0xE | RW | MMD_AD | MMD Address/Data |
| 0xF | - | reserved do no use | |
| other | - | reserved do not use |
Register CR1
| CR1 | Description |
|---|---|
| 15:12 | - |
| 11:8 | NOSEQ Mux |
| 7:4 | LED1 Mux |
| 3:0 | LED2 Mux |
Register CR2
| CR2 | Description |
|---|---|
| 15:12 | XCLK Mux |
| 11:8 | XIO6 Mux |
| 7:4 | XIO5 Mux |
| 3:0 | XIO4 Mux |
Register CR3
| CR3 bit | related function | related port/signal |
|---|---|---|
| 0 | MEMS interrupt 1 | INT1 |
| 1 | MEMS interrupt 2 | INT2 |
| 2 | Real time clock interrupt | RTC_RST |
| 3 | Interrupt output pin of ethernet transceiver | PHY_LED2 |
| 4 | Reset for high speed USB transceiver | OTG_RST |
| 5 | Reset for ethernet transceiver / Reset for serial for unio mac read core | ETH_RST |
| 6 | Reset for MMC | MMC_RST |
| 7 | Enable for ETH clock | EN_ETH_CLK |
| 15:8 | Enable for watch dog timer / Extra enable | if 0xE5 → WDT enable if 0xA5 → Extra enable |
The mapping of CPLD IOs (XIO4,XIO5,XIO6 and XCLK) that are connected directly with FPGA, can be changed using CR2 register.
Signal XIO4
| Value (CR2[3:0]) | XIO4 |
|---|---|
| 0001 | MIO7 |
| 0010 | SHA_IO |
| 0011 | MAC_IO |
| 1000 | uio_unidir |
| 0110 | 'Z' |
| 0111 | Undefined |
| Default | PHY_LED0 |
Signal XIO5
| Value (CR2[7:4]) | XIO5 | |
|---|---|---|
| 0001 | MIO14 | RX pin of UART0 (FPGA Zynq PS) |
| 0010 | Undefined | |
| 0011 | RTC_INT | |
| 1000 | uio_unidir | |
| 0110 | 'Z' | |
| 0111 | Undefined | |
| Default | PHY_LED1 |
Signal XIO6
| Value (CR2[11:8]) | XIO6 | Description |
|---|---|---|
| 0001 | MIO15 | TX pin of UART0 (FPGA Zynq PS) |
| 0010 | Undefined | |
| 0011 | osc_clk | This pin is directly connected to on-chip oscillator signal. (24.18MHZ) |
| 1000 | uio_unidir | |
| 0110 | 'Z' | |
| 0111 | INTR | INTR signal can be depending on CR3 register value connected to one of the following interrupt signals: INT1, INT2, RTC_INT, PHY_LED2 |
| Default | PHY_LED2 |
Signal XCLK
| Value (CR2[15:12]) | XCLK | Description |
|---|---|---|
| 0001 | RTC_INT | |
| 0010 | osc_clk | This pin is directly connected to on-chip oscillator signal. (24.18MHZ) |
| 0011 | Undefined | |
| 1000 | Undefined | |
| 0110 | Undefined | |
| 0111 | Undefined | |
| Default | CLK_125MHZ | This pin is connected to output clock pin of ethernet transceiver chip. |
Signal SHA_IO
| Value XIO4[3:0] | Value XIO5 | SHA_IO |
|---|---|---|
| 0010 | '0' | '0' |
| else | 'Z' | |
Signal MAC_IO
| Value XIO4[3:0] | MAC_IO |
|---|---|
| 0011 | '0' |
| else | Connected to internal MAC read block |
Signals MIO14 and MIO15
| Value (CR2[7:4]) | MIO14 | Value (CR2[11:8]) | MIO15 | Description |
|---|---|---|---|---|
| 1001 | XIO5_in | 1001 | XIO6_in | XIO5_in and XIO6_in are equal to XIO5 and XIO6 respectively if VCCIO34 voltage equal to 1.8V. |
| else | 'Z' | else | 'Z' |
Status register bits mapping:
| SR1 | Description |
|---|---|
| 0 | INT1 |
| 1 | INT2 |
| 2 | RTC_INT |
| 3 | PHY_LED2 |
| 7 | BOOTMODE_LATCHED |
| 8 | BOOTMODE_IN2 |
| 9 | BOOTMODE_IN |
| 10 | NOSEQ |
| 11 | NOSEQ_LATCHED |
| 12 | WD_EVENT |
| 13 | PG_1V5 |
| 14 | EXTRA_ENABLED or WDOG_ENABLED |
| 15 | mac_valid |
The subsystem I2C to GPIO port mapping is according the following table:
| I2C to GPIO | Pin name | CPLD Pin | Direction | FPGA Pin | Description |
|---|---|---|---|---|---|
| sda_in (SDA) | X7 | M1 | from FPGA | N22 | |
| sda_out | X5 | J1 | to FPGA | P22 | If X7 is High. If X7 is Low, this pin will be disconnected. |
| sclk (SCL) | X1 | F1 | from FPGA | L16 | |
| GPIO_input | Mapping the GPIO_input bits to various ports or signals | ||||
| GPIO_output | Not used | ||||
| GPIO_input bit | Connected to: |
|---|---|
| 0 | PHY_LED0 |
| 1 | PHY_LED1 |
| 2 | MIO7 |
| 3 | NOSEQ |
| 4 | RESIN_g |
| 5 | EN1_g |
| 6 | BOOTMODE_LATCHED |
| 7 | BOOTMODE_IN |
| 8 | INT1 |
| 9 | INT2 |
| 10 | RTC_INT |
| 11 | PHY_LED2 |
| 12 | '0' |
| 13 | '0' |
| Value (uio_sm_cnt[8:5]) | uio_io_data |
|---|---|
| 0000 | MIO7 |
| 0001 | RTC_INT |
| 0010 | INT1 |
| 0100 | INT2 |
| 0011 | PHY_LED0 |
| 0100 | PHY_LED1 |
| 0101 | PHY_LED2 |
| 0110 | BOOTMODE_IN |
| 0111 | MIO14 |
| 1000 | MIO15 |
| 1001 | XIO4 |
| 1010 | XIO5 |
| 1011 | XIO6 |
| 1100 | WD_HIT |
| 1101 | '0' |
| 1110 | '0' |
| Value (uio_sm_cnt[2:1]) | uio_unidir | Description |
|---|---|---|
| 01 | '0' | |
| 10 | uio_io_data / uio_id_data | If uio_sm_cnt(4) Low --→ uio_id_data |
On-board LEDs
There are 3 on-board LEDs, with two of them connected to the System Management Controller and one to the Zynq PL (Done pin).
| Name | Color | Connected to: | Default mapping: |
|---|---|---|---|
| LED1 | Green | SC | PL MIO[7] |
| LED2 | Red | SC | Boot Mode Blink (Fast → SPI, Slow→ SD Card) |
| LED3 | Green | Zynq PL | FPGA Done - Active Low |
LED1 Green
This LED is mapped to MIO7 after power up. After the Zynq PS has booted it can change the mapping of this LED. If SC can not enable power to the Zynq then this LED will remain under SC control. It is available to the user only after the power supplies have stabilized and the POR reset to the Zynq is released. If watch dog timer is activated this LED will be assigned to the 7th bit of the counter of watch dog timer.
| Value (CR1[3:0]) | LED1 (Green) |
|---|---|
| 0001 | PHY_LED0 |
| 0010 | PHY_LED1 |
| 0011 | PHY_LED2 |
| 0100 | MIO7 |
| 0101 | RTC_INT |
| 0110 | OFF |
| 0111 | ON |
| 1000 | XIO4 |
| 1001 | Not MIO14 |
| 1010 | Not MIO14/Not MIO15 |
| Default | MIO7 |
| LED1(Green) | Condition | Description |
|---|---|---|
| WD_counter(7) | WDOG_ENABLED = '1' | |
| ON | POR_B_i = '0' | POR_B_i is '0' if one of the following signals is '0' ---> EN1 or RESIN or PG_ALL or PORDONE |
| Variable | else | Mapping depending on the CR1[3:0] value |
LED2 Red
This LED is used to show various signal or port states. The function of this LED can be changed by CR1 register.
| Value (CR1[7:4]) | LED2 (Red) |
|---|---|
| 0001 | PHY_LED0 |
| 0010 | PHY_LED1 |
| 0011 | PHY_LED2 |
| 0100 | MIO7 |
| 0101 | RTC_INT |
| 0110 | OFF |
| 0111 | ON |
| 1000 | XIO5 |
| 1001 | Not MIO15 |
| 1010 | Not MIO14/Not MIO15 |
| Default | modeblink |
| LED2(Red) | Condition | Description |
|---|---|---|
| powerblink | EN1_g = '0' | EN1_g is delayed EN1. |
| ON | POR_B_i = '0' | |
| Variable | else | Mapping depending on the CR1[7:4] value |
LED3 Green (FPGA Done)
This green LED is connected to the FPGA Done pin which has an active low state. As soon as the Zynq is powered and the 3.3V I/O voltage is enabled, this LED will illuminate. This indicates that the Zynq PL is not configured. Once the Zynq PL has been configured the LED will go off.
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JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGENB pin of CPLD (B9) (logical one for CPLD, logical zero for FPGA). This pin is connected to B2B (JM1-pin 89) directly. On the carrier board can be this pin enabled or disabled with a dip switch.
| CPLD JTAGENB (B2B JM1-89) | Description |
|---|---|
| 0 | FPGA access |
| 1 | CPLD access |
Power
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Appx. A: Change History and Legal Notices
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Overview
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