Page History
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| Addr | R/W | Register name | Descripion |
|---|---|---|---|
| 0 | RO | ||
| 1 | RO | ||
| 2 | RO | ID1 | PHY Identifier Register 1 |
| 3 | RO | ID2 | PHY Identifier Register 2 |
| 4 | RW | ? | Auto-Negotiation advertisement register |
| 5 | RW | CR1 | Control Register 1: LED's |
| 6 | RW | CR2 | Control Register 2; XIO Control |
| 7 | RW | CR3 | Control Register 3; Reset, Interrupt |
| 8 | RO | SR1 | Status Register |
| 9 | RO | MAChi | Highest bytes of primary MAC Address |
| 0xA | RO | MACmi | Middle bytes of primary MAC Address |
| 0xB | RO | MAClo | Lowest bytes of primary MAC Address |
| 0xC | RO | CR4 | reserved do not use |
| 0xD | RW | MMD_CR | MMD Control Register |
| 0xE | RW | MMD_AD | MMD Address/Data |
| 0xF | - | reserved do no use | |
| other | - | reserved do not use |
Register CR1
| CR1 | Description |
|---|---|
| 15:12 | - |
| 11:8 | NOSEQ Mux |
| 7:4 | LED1 Mux |
| 3:0 | LED2 Mux |
Register CR2
| CR2 | Description |
|---|---|
| 15:12 | XCLK Mux |
| 11:8 | XIO6 Mux |
| 7:4 | XIO5 Mux |
| 3:0 | XIO4 Mux |
Register CR3
| CR3 bit | related function | related port/signal |
|---|---|---|
| 0 | MEMS interrupt 1 | INT1 |
| 1 | MEMS interrupt 2 | INT2 |
| 2 | Real time clock interrupt | RTC_RST |
| 3 | Interrupt output pin of ethernet transceiver | PHY_LED2 |
| 4 | Reset for high speed USB transceiver | OTG_RST |
| 5 | Reset for ethernet transceiver / Reset for serial for unio mac read core | ETH_RST |
| 6 | Reset for MMC | MMC_RST |
| 7 | Enable for ETH clock | EN_ETH_CLK |
| 15:8 | Enable for watch dog timer / Extra enable | if 0xE5 → WDT enable if 0xA5 → Extra enable |
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