Page History
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| CR3 bit | related function | related port/signal |
|---|---|---|
| 0 | MEMS interrupt 1 | INT1 |
| 1 | MEMS interrupt 2 | INT2 |
| 2 | Real time clock interrupt | RTC_RST |
| 3 | Interrupt output pin of ethernet transceiver | PHY_LED2 |
| 4 | Reset for high speed USB transceiver | OTG_RST |
| 5 | Reset for ethernet transceiver / Reset for serial for unio mac read core | ETH_RST |
| 6 | Reset for MMC | MMC_RST |
| 7 | Enable for ETH clock | EN_ETH_CLK |
| 15:8 | Enable for watch dog timer / Extra enable | if 0xE5 0xA5 → WDT enable if 0xA5 0xE5 → Extra enable |
The mapping of CPLD IOs (XIO4,XIO5,XIO6 and XCLK) that are connected directly with FPGA, can be changed using CR2 register.
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Signal XIO5
| Value (CR2[7:4]) | XIO5 | Description |
|---|---|---|
| 0001 | MIO14 | RX pin of UART0 (FPGA Zynq PS) |
| 0010 | Undefined | |
| 0011 | RTC_INT | |
| 1000 | uio_unidir | |
| 0110 | 'Z' | |
| 0111 | Undefined | |
| Default | PHY_LED1 |
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| I2C to GPIO | Pin name | CPLD Pin | Direction | FPGA Pin | Description |
|---|---|---|---|---|---|
| sda_in (SDA) | X7 | M1 | from FPGA | N22 | |
| sda_out | X5 | J1 | to FPGA | P22 | If X7 is High. If X7 is Low, this pin will be disconnected. |
| sclk (SCL) | X1 | F1 | from FPGA | L16 | |
| GPIO_input | Mapping the GPIO_input bits to various ports or signals | ||||
| GPIO_output | Not used | ||||
GPIO input bit mapping:
| GPIO_input bit | Connected to: |
|---|---|
| 0 | PHY_LED0 |
| 1 | PHY_LED1 |
| 2 | MIO7 |
| 3 | NOSEQ |
| 4 | RESIN_g |
| 5 | EN1_g |
| 6 | BOOTMODE_LATCHED |
| 7 | BOOTMODE_IN |
| 8 | INT1 |
| 9 | INT2 |
| 10 | RTC_INT |
| 11 | PHY_LED2 |
| 12 | '0' |
| 13 | '0' |
UNI/O MAC read core IO data mapping:
| Value (uio_sm_cnt[8:5]) | uio_io_data |
|---|---|
| 0000 | MIO7 |
| 0001 | RTC_INT |
| 0010 | INT1 |
| 0100 | INT2 |
| 0011 | PHY_LED0 |
| 0100 | PHY_LED1 |
| 0101 | PHY_LED2 |
| 0110 | BOOTMODE_IN |
| 0111 | MIO14 |
| 1000 | MIO15 |
| 1001 | XIO4 |
| 1010 | XIO5 |
| 1011 | XIO6 |
| 1100 | WD_HIT |
| 1101 | '0' |
| 1110 | '0' |
Multiplexing uio data output between uio-id and uio-io:
| Value (uio_sm_cnt[2:1]) | Value (uio_sm_cnt(4)) | uio_unidir |
|---|
| 01 |
| - | '0' | |
| 10 | '0' | uio |
_ |
id_data | |
| 10 | '1' |
| uio_ |
| io_data |
On-board On-board LEDs
There are 3 on-board LEDs, with two of them connected to the System Management Controller and one to the Zynq PL (Done pin).
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During normal operation when the Zynq PL has been configured, the LED can be controlled from the FPGA fabric. Control of the LED in a user design requires the use of Xilinx startup primitive rather than a normal I/O primitive. If the startup primitive is not used then the LED will go off after configuration and remain off irrespectively of the user design.
This LED can not be controlled by the SC. If green LED3 does not light up at least for short time at power then there is major problem with power supplies, FPGA core and aux voltages may be missing.
Functional Description
JTAG
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| CPLD JTAGENB (B2B JM1-89) | Description |
|---|---|
| 0 | FPGA access |
| 1 | CPLD access |
Power
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SC Firmware ver 0.05
This is the initial version of the System Controller with only a very limited function set implemented.
System Controller can be accessed as PHY with address 0x1A on the ETH0 Management bus (MIO pins 52, 53). Communication can be established anytime when ETH0 and management interface are enabled also before FPGA PL Fabric is configured. Version check!
System Controller Firmware version and some other version info can be read with u-boot command mii info:
zynq-uboot> mii info
PHY 0x00: OUI = 0x5043, Model = 0x1D, Rev = 0x01, 100baseT, FDX
PHY 0x1A: OUI = 0x7201, Model = 0x01, Rev = 0x00, 10baseT, HDX
zynq-uboot>
PHY at address 0x00 is the ETH0 onboard ethernet PHY Marvell 88E1512.
PHY at address 0x1A is the System Controller. OUI 0x7201 should be decoded as Model TE0720-01. Model 0x01 is Assembly option. Rev 0x00 is the firmware major revision for the System Controller (Rev 0 is the initial version).
Bit Decoding
| Reg Addr | Bits | U-BOOT ENV Variable | Description |
|---|---|---|---|
| 2 | 15:0 | board | upper bits of SoM Model |
| 3 | 15:10 | board | lower bits of SoM Model |
| 4 | 15:14 | board | FPGA Speed Grade (1, 2 or 3) |
| 4 | 13:12 | board | FPGA Temperature Range (0=Commercial, 1=Extended, 2=Industrial, 3=Automotive) |
| 4 | 11:8 | - | Assembly Variant |
| 4 | 7:0 | scver | SC Firmware Revision Minor number |
Customized u-boot reads and decodes the model and assembly variant information and stores in readable format in environment variables.
zynq-uboot> printenv board
board=TE0720-01-2IF
zynq-uboot>
Reading MAC Address
With u-boot command mii read:
zynq-uboot> mii read 1a 9-b
addr=1a reg=09 data=0004
addr=1a reg=0a data=A3AC
addr=1a reg=0b data=3911
zynq-uboot>
This command will read MAC Address from the System Controller. Note: This only works if the ETH0 interface is enabled and if FSBL has enabled MII Management console on ETH0 Interface. 0004A3 is OUI part, AC3911 is the serialized part (lower bits of MAC address).
Customized u-boot does read MAC Address and stores it in environment variables as required, as a result, proper MAC address is used both in u-boot as also in Linux. Setting up MAC Address for Linux involves dynamic rewrite of FDT, this is done with u-boot script that starts Linux.
Appx. A: Change History and Legal Notices
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Overview
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