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Value (CR1[11:8])NOSEQ
0001PHY_LED0
0010PHY_LED1
0011PHY_LED2
0100MIO7
0101RTC_INT
0110OFF
0111ON
1000XIO6
1001uio_unidir
1010Undefined
DefaultPHY_LED0

SC Pins to the FPGA

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AddrR/WRegister nameDescripion
0RO

1RO

2ROID1PHY Identifier Register 1
3ROID2PHY Identifier Register 2
4RW?Auto-Negotiation advertisement register
5RWCR1Control Register 1: LED's
6RWCR2Control Register 2; XIO Control
7RWCR3Control Register 3; Reset, Interrupt
8ROSR1Status Register
9ROMAChiHighest bytes of primary MAC Address
0xAROMACmiMiddle bytes of primary MAC Address
0xBROMACloLowest bytes of primary MAC Address
0xCROCR4reserved do not use
0xDRWMMD_CRMMD Control Register
0xERWMMD_ADMMD Address/Data
0xF-
reserved do no use
other-
reserved do not use


Register CR1

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CR1Descriptionrelated function
15:Enable Extra_Enable
14WD_HIT generation
13Undefined
12Undefined
11:8NOSEQ Mux
7:4LED1 Mux
3:0LED2 Mux


Register CR2

CR2Descriptionrelated function
15:12XCLK Mux
11:8XIO6 Mux
7:4XIO5 Mux
3:0XIO4 Mux

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CR3 bitrelated functionrelated port/signal
0MEMS interrupt 1INT1
1MEMS interrupt 2INT2
2Real time clock interruptRTC_RST
3Interrupt output pin of ethernet transceiverPHY_LED2
4Reset for high speed USB transceiverOTG_RST
5Reset for ethernet transceiver / Reset for serial for  unio mac read coreETH_RST
6Reset for MMCMMC_RST
7Enable for ETH clockEN_ETH_CLK
15:8Enable for watch dog timer / Extra enable

if 0xA5  → WDT enable

if 0xE5 → Extra enable


Register CR4

CR4 bitsrelated functionDescription
7:0WDT timeif CR4[7:0]=0x00 → WDT time=0x07


The mapping of CPLD IOs (XIO4,XIO5,XIO6 and XCLK) that are connected directly with FPGA, can be changed using CR2 register.  

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Value (CR2[3:0])XIO4
0001

MIO7

0010

SHA_IO

0011MAC_IO
1000uio_unidir
0110'Z'
0111Undefined
DefaultPHY_LED0


Signal XIO5

Value (CR2[7:4])XIO5Description
0001

MIO14

RX pin of UART0 (FPGA Zynq PS)
0010Undefined
0011RTC_INT
1000uio_unidir
0110'Z'
0111Undefined
DefaultPHY_LED1


Signal XIO6

Value (CR2[11:8])XIO6Description
0001

MIO15

TX pin of UART0 (FPGA Zynq PS)
0010Undefined
0011osc_clkThis pin is directly connected to on-chip oscillator signal. (24.18MHZ)
1000uio_unidir
0110'Z'
0111INTRINTR signal can be depending on CR3 register value connected to one of the following interrupt signals: INT1, INT2, RTC_INT, PHY_LED2
DefaultPHY_LED2

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Value (CR2[15:12])XCLKDescription
0001RTC_INT
0010osc_clkThis pin is directly connected to on-chip oscillator signal. (24.18MHZ)
0011Undefined
1000Undefined
0110Undefined
0111Undefined
DefaultCLK_125MHZThis pin is connected to output clock pin of ethernet transceiver chip.

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This LED can not be controlled by the SC. If green LED3 does not light up at least for short time at power then there is major problem with power supplies, FPGA core and aux voltages may be missing.

LED Status Codes

#LED1 GreenLED2 RedLED3 GreenStatusDescription
1OFFOFFONFatal power errorThis combination after power up is only possible in no sequencing compatibility mode were 3.3Vout is supplied externally. The 1.0V and 1.8V DC-DC supplies are forced on (NOSEQ=1), and the SC is not able to start (3.3Vin below 2.1V). This should never happen if the external power supplies are OK.
2OFFONOFFVIN missing (or EN1 low)3.3Vin is present, but the DC-DC supplies are not powered or 3.3Vin is below 3.05V. If the LEDs stay on in this state then 3.3Vout is not turned on, and the Zynq is kept in the POR state.
3OFF1/2 Blink Fast 4 HzONOKBoot mode selected is SPI Flash. This status remains after boot also if the LED settings are not changed and user is not controlling MIO7 and FPGA is not loaded.
4OFF1/2 Blink Slow 1 HzONOKBoot mode selected is SD Card. This status remains after boot also if the LED settings are not changed and user is not controlling MIO7 and FPGA is not loaded.
5MIO7 or user functionBlink or user functionOFFOKLED3 goes off when the FPGA is configured. NOTE: The FPGA design can control this LED too using STARTUPE2, so it may remain ON or be flashing when the FPGA is configured.
6ONSlow blink 0.5Hz, 1/8 on, 7/8 offOFFPowerdownEN1 input to the module is low. If sequencing is enabled in this mode, then all power supplies on the module are OFF.
7ONSlow blink 0.5Hz, 1/8 on, 7/8 offON
EN1 input to the module is low. Sequencing is disabled module is in reset state.
8ONONONResetPowered, RESIN input is active low or Bank B34 Supply Voltage is missing.

Functional Description

JTAG

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PHY at address 0x1A is the System Controller. OUI 0x7201 should be decoded as Model TE0720-01. Model 0x01 is Assembly option. Rev 0x00 is the firmware major revision for the System Controller (Rev 0 is the initial version).

Bit Decoding

Reg AddrBitsU-BOOT ENV VariableDescription
215:0boardupper bits of SoM Model
315:10boardlower bits of SoM Model
415:14boardFPGA Speed Grade (1, 2 or 3)
413:12boardFPGA Temperature Range (0=Commercial, 1=Extended, 2=Industrial, 3=Automotive)
411:8-Assembly Variant
47:0scverSC Firmware Revision Minor number

Customized u-boot reads and decodes the model and assembly variant information and stores in readable format in environment variables.

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