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This is a dedicated input that forces the module's 1.0V and 1.8V supplies to be enabled if high. This pin has a weak pull-down on the module. If left open the module will power up in normal power sequencing enabled mode. This pin is 3.3V tolerant. This pin is also connected to the System Management Controller. The SC can read the status of this pin (that is it can detect if the module is in power sequencing enabled mode). The SC can also use this pin as output after normal power on sequence. Please check the SC description for the function. SC rev 0.05 maps Ethernet PHY LED0 to NOSEQ by default (the mapping can be changed by software after boot).
No Sequencing mode
If the module is powered from a single 3.3V supply and power sequencing is disabled, then NOSEQ pin should be powered from the main 3.3V input. That is VIN, 3.3Vin and NOSEQ should all be tied together to the input 3.3V power rail. Sequencing mode should not be used if VIN is not 3.3V.
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| CR3 bit | related function | related port/signal |
|---|---|---|
| 0 | MEMS interrupt 1 | INT1 |
| 1 | MEMS interrupt 2 | INT2 |
| 2 | Real time clock interrupt | RTC_RST |
| 3 | Interrupt output pin of ethernet transceiver | PHY_LED2 |
| 4 | Reset for high speed USB transceiver | OTG_RST |
| 5 | Reset for ethernet transceiver / Reset for serial for unio mac read core | ETH_RST |
| 6 | Reset for MMC | MMC_RST |
| 7 | Enable for ETH clock | EN_ETH_CLK |
| 15:8 | Enable for watch dog timer / Extra enable | if 0xA5 → WDT enable if 0xE5 → Extra enable |
Register CR4
| CR4 bits | related function | Description |
|---|---|---|
| 7:0 | WDT time | if CR4[7:0]=0x00 → WDT time=0x07 |
The mapping of CPLD IOs (XIO4,XIO5,XIO6 and XCLK) that are connected directly with FPGA, can be changed using CR2 register.
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This LED can not be controlled by the SC. If green LED3 does not light up at least for short time at power then there is major problem with power supplies, FPGA core and aux voltages may be missing.
LED Status Codes
| # | LED1 Green | LED2 Red | LED3 Green | Status | Description |
|---|---|---|---|---|---|
| 1 | OFF | OFF | ON | Fatal power error | This combination after power up is only possible in no sequencing compatibility mode were 3.3Vout is supplied externally. The 1.0V and 1.8V DC-DC supplies are forced on (NOSEQ=1), and the SC is not able to start (3.3Vin below 2.1V). This should never happen if the external power supplies are OK. |
| 2 | OFF | ON | OFF | VIN missing (or EN1 low) | 3.3Vin is present, but the DC-DC supplies are not powered or 3.3Vin is below 3.05V. If the LEDs stay on in this state then 3.3Vout is not turned on, and the Zynq is kept in the POR state. |
| 3 | OFF | 1/2 Blink Fast 4 Hz | ON | OK | Boot mode selected is SPI Flash. This status remains after boot also if the LED settings are not changed and user is not controlling MIO7 and FPGA is not loaded. |
| 4 | OFF | 1/2 Blink Slow 1 Hz | ON | OK | Boot mode selected is SD Card. This status remains after boot also if the LED settings are not changed and user is not controlling MIO7 and FPGA is not loaded. |
| 5 | MIO7 or user function | Blink or user function | OFF | OK | LED3 goes off when the FPGA is configured. NOTE: The FPGA design can control this LED too using STARTUPE2, so it may remain ON or be flashing when the FPGA is configured. |
| 6 | ON | Slow blink 0.5Hz, 1/8 on, 7/8 off | OFF | Powerdown | EN1 input to the module is low. If sequencing is enabled in this mode, then all power supplies on the module are OFF. |
| 7 | ON | Slow blink 0.5Hz, 1/8 on, 7/8 off | ON | EN1 input to the module is low. Sequencing is disabled module is in reset state. | |
| 8 | ON | ON | ON | Reset | Powered, RESIN input is active low or Bank B34 Supply Voltage is missing. |
Functional Description
JTAG
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