Page History

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Products Affected

This change affects Trenz Electronic boards TE0720 of Revision 03: TE0720-03-*

Changes

#1

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Added generic options

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for PUDC and Boot Mode

Type: Enhancement
Reason: Adjustable pullup Pullup or pulldown status for IO pins and changing selectable to change the boot mode or and PUDC for custom request fastereasier.
Impact: None. Default CPLD source code is still PUDC low (Pullups Zynq pullups activated) and Boot Mode QSPI/SD.

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Type: Enhancement
Reason: HW Pulldown on carrier for Bank0 Voltage selection (3.3V)
Impact: No ImpactNone.

#3 Adding internal en_3v3_int

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Type: Enhancement
Reason: JTAG pins connected to Zynq are high impedance as long as there is no voltage in the core voltage is not available.
Impact: No Impact, improve Power sequencing

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Type: Enhancement
Reason: Boot Mode pins connected to Zynq are high impedance as long as there is no voltage in the core voltage is not available.
Impact: No Impact, improve Power sequencing

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Type: Enhancement
Reason: UART pins that to Zynq connected are high impedance as long as there is no voltage in the core voltage is not available.
Impact: No Impact, improve Power sequencing

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#9 Bugfix I2C to GPIO module (I2C_to_GPIO.v)

Type: Bugfix
Reason:   To communicate corectly with I2C to Communicate with GPIO subsystem via I2C was not possible.
Impact:  Reading and writing data from/to CPLD internal registers via I2C bus works correctly.

#10 Changed Firmware Identifier to REV06

Type:  Enhancement Update
Reason: show new Show firmware revision with Trenz FSBL.
Impact: No ImpactNone. Actual firmware revision is shown.

More information about System Controller can be found here: TE0720 System Controller.

Method of Identification

All TE0720-03 SoMs noted in the column replacement are with REV06 CPLD firmware.

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