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| Scroll pdf title |
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| title | I2C bus modes summary. |
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core | EZ-USB FX2LP | FPGA
(SDA = I/O) | B2B J(M)5 | serial EEPROM |
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default | master | slave
SCL = I | slave | slave | custom | inactive
SCL = SDA = Z | master
SCL = O | slave | slave | custom | inactive
SCL = SDA = Z | slave
SCL = I | master | slave |
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FX2 microcontroller's Interface with the IIC slave device EEPROM: it is used for firmware configuration and firmware loading in RAM from EEPROM
See Firmware configuration.
FX2 microcontroller's Interface with IIC slave device FPGA (XPS_I2C_SLAVE custom IP core block): in reference design case is used for MB Commands
TE USB FX2 module reference design includes an HDL core managing the fast mode (400 kHz) I2C communication between the Xilinx MicroBlaze embedded soft-processor and the EZ-USB FX2LP USB FX2 microcontroller.
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