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changes.mady.by.user Martin Rohrmüller

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changes.mady.by.user John Hartfiel

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MGT Lanes

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The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.

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MGT Lanes

The B2B connectors J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).

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BankTypeB2B ConnectorCount of MGT LanesSchematic Names / Connector PinsMGT Bank's Reference Clock Inputs

2241)


GTHJ1

4 GTH lanes

(4 RX / 4TX)

B224_RX3_P, B224_RX3_N, pins J1-51, J1-53
B224_TX3_P, B224_TX3_N, pins J1-50, J1-52

B224_RX2_P, B224_RX2_N, pins J1-57, J1-59
B224_TX2_P, B224_TX2_N, pins J1-56, J1-58

B224_RX1_P, B224_RX1_N, pins J1-63, J1-65
B224_TX1_P, B224_TX1_N, pins J1-62, J1-64

B224_RX0_P, B224_RX0_N, pins J1-69, J1-71
B224_TX0_P, B224_TX0_N, pins J1-68, J1-70

1 reference clock signal (B224_CLK0) from B2B connector
J3 (pins J3-59/J3-61) to bank's pins Y6/Y5

1 reference clock signal (B224_CLK1) from programmable
PLL clock generator U5 to bank's pins V6/V5

505GTRJ2

4 GTR lanes

(4 RX / 4TX)

B505_RX3_P, B505_RX3_N, pins J2-5154, J2-4952
B505_TX3_P, B505_TX3_N, pins J2-5451, J2-5249

B505_RX2_P, B505_RX2_N, pins J2-5760, J2-5558
B505_TX2_P, B505_TX2_N, pins J2-6057, J2-5855

B505_RX1_P, B505_RX1_N, pins J2-6366, J2-6164
B505_TX1_P, B505_TX1_N, pins J2-6663, J2-6461

B505_RX0_P, B505_RX0_N, pins J2-6972, J2-6770
B505_TX0_P, B505_TX0_N, pins J2-7269, J2-7067

2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector
J2 (pins J2-16/J2-18, J2-10/J2-12) to bank's pins F23/F24, E21/E22

2 reference clock signals (B505_CLK2, B505_CLK3) from programmable
PLL clock generator U5 to bank's pins C21/C22, A21/A22

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 DateRevisionContributorsDescription

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infoTypeCurrent version
dateFormatyyyy-MM-dd
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infoTypeModified by
typeFlat

  • typo
  • fixed MGT Lanes RX/TX order
2019-07-15v.36John Hartfiel
  • correction SPLL section
2019-07-02v.35John Hartfiel
  • add eeprom section
  • update PCB Revision section
2019-06-19v.33John Hartfiel
  • update links
  • correction flash section

2018-08-20

v.29John Hartfiel
  • power section: add missing PS_1V8 output pin

2018-08-06

v.28John Hartfiel
  • typo correction
2017-11-13v.23Ali Naseri
  • updated B2B connector max. current rating per pin

2017-11-13

v.19



John Hartfiel
  • rework B2B section
2017-10-19

v.18

John Hartfiel
  • Removed ES1 Note
2017-08-15v.17Vitali Tsiukala
  • Changed Signals Count in the table B2B-connectors

2017-08-07


v.14

Jan Kumann
  • New smaller images.
  • New QSPI Flash MIO mapping table.
  • Temperature information changes.
  • Few corrections.

2017-05-17

V.4


Ali NaseriCurrent TRM release.
2017-05-10v.1Ali NaseriInitial document.

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