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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
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title | Text |
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Important General Note:
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Overview
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Linux with basic periphery of TE0818 StarterKit (TEBF0818 Carrier).
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
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title | Text |
Overview
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scroll-office | true |
scroll-chm | true |
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Linux with basic periphery of TE0818 StarterKit (TEBF0818 Carrier).
Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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title | Design Revision History |
TE0813-StarterKit_noprebuilt-vivado_2020.2-build_8_20211028142614.zip
- initial release
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| Known Issues
| Description | Workaround/Solution | To be fixed version | ||||||||||||||||||||||||||||||||
QSPI Flash | Programming QSPI flash fails sometimes | use Vivado 2019.2 for programming | -- |
Requirements
Software
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title-alignment | center |
title | Software |
Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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title | Hardware Modules |
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Release Notes and Know Issues
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Requirements
Software
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*used as reference
Note: Design contains also Board Part Files for TE0818 only configuration, this board part files are not used for this reference design.
Design supports following carriers:Scroll Title | ||||||||||||||||||
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TEBF0818* | Used as reference carrier. |
Additional HW Requirements:
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title-alignment | center |
title | Additional Hardware |
Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL P2421
Can be used to get access to console which is show on DP
USB was tested with USB memory stick
Ethernet works with DHCP, but can be setup also manually
Content
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
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<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Additional Sources
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title-alignment | center |
title | Additional design sources |
Prebuilt
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id | Comments |
Notes :
anchor | Table_PF |
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title-alignment | center |
title | Prebuilt files |
File
File-Extension
Description
Distro Boot file
Debian SD-Image
*.img
Debian Image for SD-Card
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
anchor | Table_PF |
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title-alignment | center |
title | Prebuilt files (only on ZIP with prebult content) |
File
File-Extension
Description
Distro Boot file
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide) |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
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Note: Select correct one, see also Vivado Board Part Flow
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Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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TE::hw_build_design -export_prebuilt |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info |
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"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
Generate Programming Files with Vitis
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TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
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TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Launch
scroll-pdf | true |
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scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
Select create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
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TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0813 (optional) |
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To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Depends on Carrier, see carrier TRM.
- TEBF0818 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
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Note: See TRM of the Carrier, which is used. |
Tip |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
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1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
Linux
Open Serial Console (e.g. putty)select COM Port
Info |
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Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
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petalinux login: root
Password: root |
Info |
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Note: Wait until Linux boot finished |
You can use Linux shell now.
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide)
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
- Important: Use Board Part Files, which ends with *_tebf0818
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0813
- Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0818 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area
SD-Boot mode
- Copy image.ub, boot.src and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (JTAG XMOD)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr- (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional) Connect SATA Disc
- (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional) Connect Network Cable
Power On PCB
Expand title boot process 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password disabled petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight i2cdetect -y -r 0 (check I2C Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to Zynq
Vivado Hardware Manager
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i2cdetect -y -r 0 (check I2C Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB check)
lspci (PCIe check) |
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Vivado Hardware Manager
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Note:
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD
- Set Enable to send Write date over RGPIO interface.
anchor | Figure_VHM |
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title-alignment | center |
title | Vivado Hardware Manager |
Image Removed
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System Design - Vivado
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Block Design
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Activated interfaces:
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title | PS Interfaces |
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0818+CPLD
- Set Enable to send Write date over RGPIO interface.
- Control:
- LEDs: XMOD 2 (without green dot) and HD LED are accessible.
- CAN_S
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System Design - Vivado
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Block Design
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PS Interfaces
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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#TEBF0818 # system controller ip #LED_HD SC0 J3:C13 #LED_XMOD SC17 J3:B19 #CAN RX SC19 J3:B23 B26_L11L2_P #CAN TX SC18 J3:B22 B26_L11L2_N #CAN S SC16 J3:B18 B26_L1L3_N set_property PACKAGE_PIN J14 [get_ports BASE_sc0] set_property PACKAGE_PIN F15 [get_ports BASE_sc5] set_property PACKAGE_PIN H13 [get_ports BASE_sc6] set_property PACKAGE_PIN H14 [get_ports BASE_sc7] set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B15 [get_ports BASE_sc11] set_property PACKAGE_PIN C13 [get_ports BASE_sc12] set_property PACKAGE_PIN C14 [get_ports BASE_sc13] set_property PACKAGE_PIN E13 [get_ports BASE_sc14] set_property PACKAGE_PIN E14 [get_ports BASE_sc15] set_property PACKAGE_PIN A13 [get_ports BASE_sc16] set_property PACKAGE_PIN B13 [get_ports BASE_sc17] set_property PACKAGE_PIN A14 [get_ports BASE_sc18] set_property PACKAGE_PIN B14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # Audio Codec #LRCLK J3:D22 #BCLK J3:D23 #DAC_SDATA J3:C21 #ADC_SDATA J3:C22 set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ] set_property PACKAGE_PIN G15 [get_ports I2S_bclk ] set_property PACKAGE_PIN F13 [get_ports I2S_sdin ] set_property PACKAGE_PIN G13 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20202023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20202023.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL ---------------------------------------------------------- fsblTE modified 2023.2 FSBL GeneralGeneral:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
---------------------------------------------------------- zynqmp_fsblZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2023TE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwpmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example:Xilinx default PMU firmware. ----------------------------------------------------------General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
zynqmp_fsbl
TE modified 20202023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_
fsbl_flashpmufw
Xilinx default PMU firmware.
hello_te0813
Hello TE0813 is
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0813
Hello TE0813 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Activate:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_
- FLASH_PSU_
- QSPI_
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
- CONFIG_SD_BOOT=y
Change platform-top.h:
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- 0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0813_TEBF0818"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_NVMEM=y
- CONFIG_DM_RTC=y (needed for nvmem driver because of bug in uboot)
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
- Identification
- CONFIG_IDENT_STRING=" TE0813_TEBF0818"
Change platform-top.h:
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/include/ "system-conf.dtsi"
/*------------------ gtr --------------------*/
//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
/ {
refclk3:psgtr_dp_clock {
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Device Tree
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/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /* notes: serdes: https://patchwork.kernel.org/project/linux-arm-kernel/patch/1536769366-31398-2-git-send-email-anurag.kumar.vulisha@xilinx.com/ https://github.com/Xilinx/linux-xlnx/blob/master/include/dt-bindings/phy/phy.h */ /* default */ /* sata */ &sata { phy-names = "sata-phy"; phys = <&lane2 1 0 0 150000000>; //+phys = <PHANDLE CONTROLLER_TYPE CONTROLLER_INSTANCE LANE_REF_CLK LANE_FREQ>; //+ //+PHANDLE = &lane0 or &lane1 or &lane2 or &lane3 //+CONTROLLER_TYPE = PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB //+ or PHY_TYPE_DP or PHY_TYPE_SGMII //+CONTROLLER_INSTANCE = Depends on controller type used, can be any of //+ PHY_TYPE_PCIE : 0 or 1 or 2 or 3 //+ PHY_TYPE_SATA : 0 or 1 //+ PHY_TYPE_USB : 0 or 1 //+ PHY_TYPE_DP : 0 or 1 //+ PHY_TYPE_SGMII: 0 or 1 or 2 or 3 //+LANE_REF_CLK compatible = Depends on which lane clock is used as ref clk, can be //+ 0 or 1 or 2 or 3 //+LANE_FREQ"fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; = Frequency of the reference clock, can be any of the //+ below mentioned based on the phy type used //+- PHY_TYPE_PCIE}; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = 100Mhz //+- PHY_TYPE_SGMII<0x00>; clock-frequency = 125Mhz //+- PHY_TYPE_SATA<100000000>; }; refclk1:psgtr_sata_clock { compatible = 125Mhz, 150Mhz //+- PHY_TYPE_USB"fixed-clock"; #clock-cells = 26Mhz, 52Mhz, 100Mhz //+- PHY_TYPE_DP<0x00>; clock-frequency = 27Mhz, 108Mhz, 135Mhz <150000000>; }; /* SD */ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; phys = <&lane1 4 0 2 100000000>; maximum-speed = "super-speed"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; refclk0:psgtr_unused_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; }; &psgtr { clocks = <&refclk0 &refclk1 &refclk2 &refclk3>; //clocks = <&refclk0 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref0\0ref1\0ref2\0ref3"; }; /*------------------ SD --------------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /*------------------- USB --------------------*/ &dwc3_0 { status = "okay"; flash0: flash@0 { compatibledr_mode = "jedec,spi-norhost"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*------------------ ETH #address-cells = <1>; PHY --------------------*/ &gem3 { /delete-property/ local-mac-address; #sizephy-cellshandle = <0><&phy0>; regnvmem-cells = <0x73><ð0_addr>; nvmem-cell-names = i2c-mux-idle-disconnect;"mac-address"; i2c@0 { // MCLK TEBF0818 SI5338A, 570FBB000290DG_unassembledphy0: phy0@1 { #address-cellsdevice_type = <1>; #size-cells = <0>; "ethernet-phy"; reg = <0><1>; }; }; /*----------------- SATA PHY --------------------*/ &sata { i2c@1 { // SFP TEBF0818 PCF8574DWR ceva,p0-burst-params = <0x13084a06>; ceva,p0-cominit-params = <0x18401828>; #address-cellsceva,p0-comwake-params = <1><0x614080e>; ceva,p0-retry-params = <0x96a43ffc>; #size-cellsceva,p1-burst-params = <0><0x13084a06>; ceva,p1-cominit-params = <0x18401828>; regceva,p1-comwake-params = <1><0x614080e>; ceva,p1-retry-params = <0x96a43ffc>; }; /*-------------------- i2c@2 { // PCIe QSPI ---------------------*/ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 reg{ = <2>; compatible }= "jedec,spi-nor"; i2c@3reg { // SFP1 TEBF0818 = <0x0>; #address-cells = <1>; #size-cells = <0><1>; reg = <3>; }; i2c@4 {// SFP2 TEBF0818 #address-cellsspi-rx-bus-width = <1><4>; #size-cellsspi-tx-bus-width = <0><4>; spi-max-frequency = <90000000>; reg = <4>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 }; { // u i2c@5 { //compatible TEBF0818 EEPROM = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; reg = <5> i2c-mux-idle-disconnect; i2c@0 { // MCLK eeprom:TEBF0818 eeprom@50 { SI5338A, 570FBB000290DG_unassembled compatiblereg = "atmel,24c08"<0>; }; i2c@1 { // regSFP =TEBF0818 <0x50>; PCF8574DWR reg = }<1>; }; i2c@6i2c@2 { // TEBF0818 FMC PCIe #address-cellsreg = <1><2>; }; i2c@3 { #size-cells = <0>;// SFP1 TEBF0818 reg = <6><3>; }; i2c@7i2c@4 { // SFP2 TEBF0818 USB HUB #address-cellsreg = <1><4>; }; i2c@5 { #size-cells = <0>;// TEBF0818 EEPROM reg = <7><5>; }; eeprom: eeprom@50 };{ i2cswitch@77 { // u compatible = "nxpmicrochip,pca954824aa025"; #address-cells = <1>, "atmel,24c02"; #size-cells = <0>; reg = <0x77><0x50>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0818 PMOD P1 #address-cells = <1>; #size-cells = <0><1>; reg = <0>;eth0_addr: eth-mac-addr@FA { }; i2c@1 { //reg i2c= Audio<0xFA Codec0x06>; #address-cells = <1>}; }; #size-cells = <0>; }; regi2c@6 = <1>; /*{ // TEBF0818 FMC adau1761:reg adau1761@38= {<6>; }; compatiblei2c@7 = "adi,adau1761"; { // TEBF0818 USB HUB reg = <0x38><7>; }; }; */ i2cswitch@77 { // u }; compatible i2c@2 { // TEBF0818 Firefly A = "nxp,pca9548"; reg = <0x77>; #address-cells = <1> i2c-mux-idle-disconnect; i2c@0 { // TEBF0818 #size-cells = <0>;PMOD P1 reg = <2><0>; }; i2c@3i2c@1 { // TEBF0818i2c FireflyAudio BCodec #address-cellsreg = <1>; #size-cells = <0>;/* regadau1761: =adau1761@38 <3>;{ }; compatible i2c@4 { //Module PLL Si5338 or SI5345 = "adi,adau1761"; #address-cellsreg = <1><0x38>; #size-cells = <0>}; reg = <4>;*/ }; i2c@5i2c@2 { // TEBF0818 CPLDFirefly A #address-cellsreg = <1><2>; }; i2c@3 { // #size-cellsTEBF0818 =Firefly <0>;B reg = <5><3>; }; i2c@6i2c@4 { //TEBF0818 Firefly PCF8574DWRModule PLL Si5338 or SI5345 #address-cellsreg = <1><4>; }; i2c@5 #size-cells = <0>;{ //TEBF0818 CPLD reg = <6><5>; }; i2c@7i2c@6 { // TEBF0818 PMODFirefly P3PCF8574DWR #address-cellsreg = <1><6>; }; i2c@7 { // #size-cellsTEBF0818 =PMOD <0>;P3 reg = <7>; }; }; }; |
Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
- # CONFIG_CPU
- _FREQ is not set
- Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_VERBOSE_ERRORS is not set
- # CONFIG_NVME_HWMON is not set
- # CONFIG_NVME_AUTH is not set
- CONFIG_NVME_
- TARGET=y
- # CONFIG_
- NVME_
- TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET
- _LOOP is not set
- # CONFIG_
CONFIG_SATA_MOBILE_LPM_POLICY=0
CONFIG_NVM=y
CONFIG_NVM_PBLK=y
CONFIG_NVM_PBLK_DEBUG=y
- NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
- # CONFIG_NVME_TARGET_AUTH is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
Rootfs
Start with petalinux-config -c rootfsChanges
Changes:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools
- =y
- CONFIG_packagegroup-petalinux-utils=
- y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils
- ,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_imagefeature-serial-autologin-root=y
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
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Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq ZynqMP access. Need busybox-httpd
Additional Software
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SI5338
File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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