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LEDColorConnected toDescription and Notes
D1GreenLED2User configurable LED.
D2RedLED1User configurable LED.
D3GreenDONE

Reflects inverted DONE signal, ON when FPGA is not configured, OFF as soon as PL is configured.

This LED will not operate if the the 3.3V power rail is not available.

After FPGA configuration the user can use USRACCESSE2 to control Done LED.

D4GreenC_LED

Connected to the system controller indicating status of the module:

Steadily lit: RESIN pin is kept low.

Blinking fast (0.1s on/off): Power sequencing fault (PG_ALL = 0).

Blinking at medium speed (0.5s on/off): Power sequencing has completed but the FPGA is not configured (PG_ALL = 1, DONE = 0).

Blinking slow (1s on/off): FPGA is configured and board is ready (PG_ALL = 1, DONE = 1).

It is also possible to program the System Controller CPLD to connect this LED to FPGA pin named XIO.

, functionalitly, see: TE0741 CPLD#LED


Table 5: Description of the on board LED's.

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DateRevisionContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • update LED description
2018-08-29v.64John Hartfiel
  • update CPLD description and links

2017-11-10

Nov 2017

v.63John Hartfiel
  • Replace B2B connector section
2017-08-28v.60Jan Kumann
  • New power-on diagram.
  • Few improvements.
  • Template revision added.
2017-07-20

v.57

John Hartfiel
  • Correction: PLL  default output CLKs.
2017-06-07v.55Jan Kumann
  • Minor formatting
2017-06-02

v.50

Jan Kumann

  • REV03 specific update.
2017-01-22

v.42

Jan Kumann
  • New block diagram added.
2017-01-13

v.38

Jan Kumann

  • New product images and physical dimension drawings.
  • Formatting improvements and small corrections.
2017-01-12

v.21

John Hartfiel
  • Correction: B2B  and FPGA bank location.
2016-12-14

v.19

Ali Naseri

  • TRM revision.
2013-12-02v.1

Antti Lukats, Jon Bean

  • Initial version.

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