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LED | Color | Connected to | Description and Notes |
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D1 | Green | LED2 | User configurable LED. |
D2 | Red | LED1 | User configurable LED. |
D3 | Green | DONE | Reflects inverted DONE signal, ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the the 3.3V power rail is not available. After FPGA configuration the user can use USRACCESSE2 to control Done LED. |
D4 | Green | C_LED | Connected to the system controller indicating status of the module: Steadily lit: RESIN pin is kept low. Blinking fast (0.1s on/off): Power sequencing fault (PG_ALL = 0). Blinking at medium speed (0.5s on/off): Power sequencing has completed but the FPGA is not configured (PG_ALL = 1, DONE = 0). Blinking slow (1s on/off): FPGA is configured and board is ready (PG_ALL = 1, DONE = 1). It is also possible to program the System Controller CPLD to connect this LED to FPGA pin named XIO. , functionalitly, see: TE0741 CPLD#LED |
Table 5: Description of the on board LED's.
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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2018-08-29 | v.64 | John Hartfiel |
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2017-11-10 | v.63 | John Hartfiel |
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2017-08-28 | v.60 | Jan Kumann |
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2017-07-20 | v.57 | John Hartfiel |
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2017-06-07 | v.55 | Jan Kumann |
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2017-06-02 | v.50 | Jan Kumann |
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2017-01-22 | v.42 | Jan Kumann |
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2017-01-13 | v.38 | Jan Kumann |
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2017-01-12 | v.21 | John Hartfiel |
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2016-12-14 | v.19 | Ali Naseri |
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2013-12-02 | v.1 | Antti Lukats, Jon Bean |
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