Page History

Overview

Refer to http://trenz.org/te0817-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Note: Design contains also Board Part Files for TE0817 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - Xilinx AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0817 "Starterkit" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"
3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow

     
     

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

   
   

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

7. Generate Programming Files with Vitis
   1. Copy PetaLinux build image files to prebuilt folder
      1. copy u-boot.elf,
   u-boot
   1. 1. system.dtb,
   system
   1. 1. bl31.
   dtb
   1. 1. elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
         

         Info
         "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

         
         

         Page properties
         hidden true id Comments
         This step depends on Xilinx Device/Hardware for Zynq-7000 series copy u-boot.elf,

   u-boot.dtb, system

   1. 1. system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for ZynqMP copy u-boot.elf,

   u-boot.dtb,

   1. 1. system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder for Microblaze ...

   Generate

   1. 1. 
         
         

   2.  Generate Programming Files
   with Vitis

   1. Code Block
      language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

      
      

      Note
      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

      
      

8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

Option for Boot.bin on QSPI Flash

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp hello_te0817

   
   

3. Set Boot Mode to QSPI-Boot.
   
   • Depends on Carrier, see carrier TRM.

SD-Boot mode

1. Copy image.ub, boot.src and Boot.bin on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. (Optional with TEBF0818) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
5. (Optional with TEBF0818) Connect SATA Disc
6. (Optional with TEBF0818) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
7. (Optional with TEBF0818) Connect Network Cable

8. Power On PCB

   Expand
   title boot process
   1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

   Page properties
   hidden true id Comments
   This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze with Linux 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ...

   
   

Linux

1. Open Serial Console (e.g. putty)
   
   • Speed: 115200

   • select COM Port

     Info
     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

     
     

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   # password default disabled with 2021.2 petalinux release petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)

   
   

4. Option Features

   • Webserver to get access to ZynqMP
     • insert IP on web browser to start web interface
   • init.sh scripts
     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
       

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
  

  • Set Enable to send Write date over RGPIO interface. 
    • CPLD Description: TEBF0818 CPLD
      • Buttons, LEDs, Status...

• Control:
  • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
  • CAN_S
    

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title-alignment center title Block Design
Image RemovedImage Added

PS Interfaces

Activated interfaces:

Constraints

Basic module constraints

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constraints

#System Controller IP
#HDIO_SC0  J3:C13  LED_HD
#HDIO_SC1  J3:C14
#HDIO_SC2  J3:D14
#HDIO_SC3  J3:D15
#HDIO_SC4  J3:D18
#HDIO_SC5  J3:D19
#HDIO_SC6  J3:C17
#HDIO_SC7  J3:C18
#HDIO_SC10  J3:A13
#HDIO_SC11  J3:A14
#HDIO_SC12  J3:B14
#HDIO_SC13  J3:B15
#HDIO_SC14  J3:A17
#HDIO_SC15  J3:A18
#HDIO_SC16  J3:B18  CAN S
#HDIO_SC17  J3:B19  LED_XMOD 
#HDIO_SC18  J3:B22  CAN TX 
#HDIO_SC19  J3:B23  CAN RX


set_property PACKAGE_PIN A13 [get_ports BASE_sc0]
set_property PACKAGE_PIN D14 [get_ports BASE_sc5]
set_property PACKAGE_PIN B14 [get_ports BASE_sc6]
set_property PACKAGE_PIN C14 [get_ports BASE_sc7]

set_property PACKAGE_PIN K11 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN K12 [get_ports BASE_sc11]
set_property PACKAGE_PIN G14 [get_ports BASE_sc12]
set_property PACKAGE_PIN H14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
set_property PACKAGE_PIN H12 [get_ports BASE_sc16]
set_property PACKAGE_PIN H13 [get_ports BASE_sc17]
set_property PACKAGE_PIN J12 [get_ports BASE_sc18]
set_property PACKAGE_PIN K13 [get_ports BASE_sc19]

set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

# PLL
#J4:A28 B64_L14_P
#set_property PACKAGE_PIN AF17 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]



# Audio Codec
#LRCLK      J3:D22 B47_L9_N
#BCLK       J3:D23 B47_L9_P
#DAC_SDATA  J3:C21 B47_L7_N
#ADC_SDATA  J3:C22 B47_L7_P

set_property PACKAGE_PIN C12 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN D12 [get_ports I2S_bclk ]
set_property PACKAGE_PIN E13 [get_ports I2S_sdin ]
set_property PACKAGE_PIN E14 [get_ports I2S_sdout ]

set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

  

Software Design - Vitis

# MGTs
#   R8    MGT_224_CLK0_P -> B2B,J3-B27 -> TEBF0818-01_FMC_J5E-D5
#   R7    MGT_224_CLK0_N -> B2B,J3-B26 -> TEBF0818-01_FMC_J5E-D4
#   N8    MGT_224_CLK1_P -> U5,38 -> Si5345 -> out4
#   N7    MGT_224_CLK1_N -> U5,37 -> Si5345 -> out4

#   L8    MGT_225_CLK0_P -> B2B,J3-C26 -> TEBF0818-01_FMC_J5E-B21
#   L7    MGT_225_CLK0_N -> B2B,J3-C25 -> TEBF0818-01_FMC_J5E-B20
#   J8    MGT_225_CLK1_P -> U5,35 -> Si5345 -> out3
#   J7    MGT_225_CLK1_N -> U5,34 -> Si5345 -> out3

#   H10   MGT_226_CLK0_P -> U5,31 -> Si5345 -> out2
#   H9    MGT_226_CLK0_N -> U5,30 -> Si5345 -> out2
#   F10   MGT_226_CLK1_P -> B2B,J3-D27 -> TEBF0818-01_CLK7_P -> B2B,J2-D5 -> U5,51 -> Si5345 -> out7
#   F9    MGT_226_CLK1_N -> B2B,J3-D26 -> TEBF0818-01_CLK7_N -> B2B,J2-D6 -> U5,50 -> Si5345 -> out7

#   D10   MGT_227_CLK0_P -> U5,28 -> Si5345 -> out1
#   D9    MGT_227_CLK0_N -> U5,27 -> Si5345 -> out1
#   B10   MGT_227_CLK1_P -> B2B,J2-A6 -> floating
#   B9    MGT_227_CLK1_N -> B2B,J2-A7 -> floating

set_property PACKAGE_PIN R8   [get_ports {MGT_CLK_IN_clk_p[0]}]
set_property PACKAGE_PIN N8   [get_ports {MGT_CLK_IN_clk_p[1]}]
set_property PACKAGE_PIN L8   [get_ports {MGT_CLK_IN_clk_p[2]}]
set_property PACKAGE_PIN J8   [get_ports {MGT_CLK_IN_clk_p[3]}]
set_property PACKAGE_PIN H10  [get_ports {MGT_CLK_IN_clk_p[4]}]
set_property PACKAGE_PIN F10  [get_ports {MGT_CLK_IN_clk_p[5]}]
set_property PACKAGE_PIN D10  [get_ports {MGT_CLK_IN_clk_p[6]}]
set_property PACKAGE_PIN B10  [get_ports {MGT_CLK_IN_clk_p[7]}]   

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5345 Configuration
  • OTG+PCIe Reset over MIO
  • I2C MUX for EEPROM MAC

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set Boot Mode to JTAG

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0817

Hello TE0817 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• select SD default instead of eMMC:
  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• generate u-boot.dtb:
  •  CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000

U-Boot

Start with petalinux-config -c u-boot

Changes:

• MAC from eeprom together with uboot and device tree settings:
  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
  • CONFIG_SYS_I2C_EEPROM_BUS=7
• Boot Modes:
  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • # CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000

Change platform-top.h:

#include <configs/xilinx_zynqmp.h>
#no changes

Device Tree

zynqmp_fsbl

TE modified 2022.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5345 Configuration
  • OTG+PCIe Reset over MIO
  • I2C MUX for EEPROM MAC

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0817

Hello TE0817 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• select SD default instead of eMMC:
  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
• Identification
  • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
  • CONFIG_SUBSYSTEM_PRODUCT="TE0817_TEBF0818"

U-Boot

Start with petalinux-config -c u-boot

Changes:

• MAC from eeprom together with uboot and device tree settings:
  
  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_ZYNQ_MAC_IN_EEPROM is not set
  • CONFIG_NET_RANDOM_ETHADDR is not set
• Boot Modes:
  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_IN_FAT is not set
  • CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000
• Identification
  • CONFIG_IDENT_STRING=" TE0817"

Change platform-top.h:

#include <configs/xilinx_zynqmp.h>
#no changes

Device Tree

/include/ "system-conf.dtsi"


/*------------------ gtr --------------------*/

//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
 
/ {
  refclk3:psgtr_dp_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <27000000>;
  };
   
   refclk2:psgtr_pcie_usb_clock {
           compatible = "fixed-clock";
           #clock-cells = <0x00>;
           clock-frequency = <100000000>;
   };
    
  refclk1:psgtr_sata_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <150000000>;
  };
    
  //refclk0:psgtr_unused_clock {
  //        compatible = "fixed-clock";
  //        #clock-cells = <0x00>;
  //        clock-frequency = <100000000>;
  //};
};
 
&psgtr {
  clocks =  #clock-cells = <0x00><&refclk1 &refclk2 &refclk3>;
  //* ref clk instances used per lane */
  clock-frequencynames = <100000000>"ref1\0ref2\0ref3";
};
 
 //};
};
 
&psgtr {
  clocks = <&refclk1 &refclk2 &refclk3>;
  /* ref clk instances used per lane */
  clock-names = "ref1\0ref2\0ref3";
};
 
 
/*------------------ SD --------------------*/
&sdhci0 {
    // disable-wp;
    no-1-8-v;
 
};
 
&sdhci1 {
    // disable-wp;
    no-1-8-v;
 
};
 
 
/*------------------ SDUSB --------------------*/
&sdhci0dwc3_0 {
    status // disable-wp= "okay";
    no-1-8-vdr_mode = "host";
  
};
 
&sdhci1 {
    // disable-wp  snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    no-1-8-v;
 
maximum-speed = "super-speed";
};
 
 
/*------------------ USBETH PHY --------------------*/
&dwc3_0gem3 {
    statusphy-handle = "okay";<&phy0>;
    
    dr_modenvmem-cells = "host"<&eth0_addr>;
    snps,usb3_lpm_capablenvmem-cell-names = "mac-address";
    snps,dis_u3_susphy_quirk;

     snps,dis_u2_susphy_quirk;
phy0: phy0@1 {
       phy-names device_type = "usb2-phy","usb3ethernet-phy";
    maximum-speed    reg = "super-speed"<1>;
    }; };


/*------------------ ETHSATA PHY --------------------*/
&gem3sata {

			ceva,p0-burst-params = <0x13084a06>;
			ceva,p0-cominit-params  phy-handle= <0x18401828>;
			ceva,p0-comwake-params = <&phy0><0x614080e>;
			ceva,p0-retry-params =   
    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";
    
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};
 <0x96a43ffc>;
			ceva,p1-burst-params = <0x13084a06>;
			ceva,p1-cominit-params = <0x18401828>;
			ceva,p1-comwake-params = <0x614080e>;
			ceva,p1-retry-params = <0x96a43ffc>;

};


/*------------------ QSPI --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/*------------------ I2C --------------------*/
&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            reg = <0>;
        };
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            reg = <1>;
        };
        i2c@2 { // PCIe
            reg = <2>;
        };
        i2c@3 { // SFP1 TEBF0808
            reg = <3>;
        };
        i2c@4 {// SFP2 TEBF0808
            reg = <4>;
        };
        i2c@5 { // TEBF0808 EEPROM
            reg = <5>;
            eeprom: eeprom@50 {
                compatible = "microchip,24aa025", "atmel,24c02";
                reg = <0x50>;
                
                #address-cells = <1>;
                #size-cells = <1>;
                eth0_addr: eth-mac-addr@FA {
                  reg = <0xFA 0x06>;
                };
           };
        };
        i2c@6 { // TEBF0808 FMC 
            reg = <6>;
        };
        i2c@7 { // TEBF0808 USB HUB
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0808 PMOD P1
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            reg = <1>;
            /*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
            */
        };
        i2c@2 { // TEBF0808 Firefly A
            reg = <2>;
        };
        i2c@3 { // TEBF0808 Firefly B
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 or SI5345
            reg = <4>;
        };
        i2c@5 { //TEBF0808 CPLD
            reg = <5>;
        };
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            reg = <6>;
        };
        i2c@7 { // TEBF0808 PMOD P3
            reg = <7>;
        };
    };
};
  

FSBL patch

Kernel

Start with petalinux-config -c kernel

Changes:

• Only needed to fix JTAG Debug issue:# CONFIG:_CPU_IDLE is not set
  
  • # CONFIG_CPU_FREQ is not set
  • CONFIG_EDAC_CORTEX_ARM64=y
• Support PCIe memory card
  • CONFIG_NVME_CORE=y
  • CONFIG_BLK_DEV_NVME=y
  • # CONFIG_NVME_MULTIPATH is not set
  • # CONFIG_NVME_HWMON is not set
  • # CONFIG_NVME_TCP is not set
  • CONFIG_NVME_TARGET=y
  • # CONFIG_NVME_TARGET_PASSTHRU is not set
  • # CONFIG_NVME_TARGET_LOOP is not set
  • # CONFIG_NVME_TARGET_FC is not set
  • # CONFIG_NVME_TARGET_TCP is not set
  • CONFIG_SATA_AHCI=y
  • CONFIG_SATA_MOBILE_LPM_POLICY=0
  • CONFIG_NVM=y
  • CONFIG_NVM_PBLK=y
  • CONFIG_NVM_PBLK_DEBUG=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

• For web server app:
  • CONFIG_busybox-httpd=y
• For additional test tools only:
  • CONFIG_i2c-tools=y
  • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
• For auto login:
  • CONFIG_auto-login=y
  • CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for ZynqMP access. Need busybox-httpd

Additional Software

SI5345

File location "<project folder>\misc\PLL\Si5345_D\Si5345-*.slabtimeproj"

General documentation how you work with this project will be available on Si5345

App. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

Legal Notices