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1 Overview

This guide showcases the important components of the module-carrier combination TE0717 + TEB0717 and introduces the available script-based reference design to get the board up and running.

1.1 Prerequisites

1.2 Getting Started with the TE0717

The module TE0717 has a Xilinx Spartan-7 FPGA onboard that allows you to create extensive digital hardware and software designs.

Most of the FPGA IOs are spread arround the carrier. The TE0717 is assembled with HyperRAM(64 Mbit), QSPI non-volatile Flash memory(64 Mbit) and plenty of IOs which enable great hardware expandability. For communication and configuration the carrier offers a JTAG/UART Interface.

This Getting Started Guide shows how to set up the board, attach the jumpers, wire it up and connect it with the software. Over the course of this guide we will go into "how to use the provided reference design" and touch several aspects of "how to modify the design according to your needs". This includes changing the Vivado Block Design, regenerating the bitstream and using the hardware export(.xsa file) in Vitis to develop software that runs on the MicroBlaze. We will not build the whole project from scratch here since that would go beyond the scope of this guide.

• hardware setup
• not from scratch, sprengt den umfang
• introduce refrerence design wth microblaze
• make the board output Hello Trenz via Microblaze
• how you can use the vivado tools to modify designfiles according to your application needs
• Features used in the referemce design

..... .....

1.3 Official Documentation

• Official links to the shop:
• Technical Reference Manual:
  
• Reference Designs - Description and Download:
  • TE0717 Reference Designs

1.4 TE0717 module + TEB0717 carrier - Hardware Features

• FPGA
  • Xilinx Spartan-7 - XC7S25-1FTGB196C
• Clocking
  • 100 MHz clock from clocking chip SiT8008 on TE0717 module
• Memory
  • 8 MByte DDR HyperRAM
  • 8 MByte Quad-SPI Flash
• Communication
  • On carrier USB-JTAGProgramming
• Connectors
  • B2B connector - Module(JM1) to Carrier(JB1)
  • Unpopulated PIN Header on carrier(J3, J4, J5)
• Configuration and Debug
  • On carrier USB-JTAGinterface
• Jumper
  • Adjustable BANK34 supply voltage (J2)
  • Power source (J1)
• General Purpose I/O
  • 2x2 user LEDs (red,green)

Basic IOs<->FPGA connections are as following, Table 1:

Hands-On

2.1 TE0717 Hardware Setup and Power up

1. Before connecting the Board to the PC, make sure to properly mount the module TE0717 onto the carrier TEB0717 via the B2B connector like Figure 1.
2. Check the Jumper setting
   
   
   Figure 3: Jumper setting
   

   The Voltage set with Jumper J1 determines the source of the input voltage for the voltages regulator chip U1. Either 5V from the MicroUSB port or 5V from pin header J4.

   With Jumper J2 the voltage VADJ is set to 3.3V that comes from the carriers voltage regulator chip U1. The 1.8V comes from the module. The Voltage VADJ is wired to the module and is used as the BANK34 supply voltage.

3. Use a MicroUSB cable to connect your board to the PC.

4. All the LEDs are simply routed to the FPGA, hence none of them should be turned on. If the qspi flash on the module is preloaded with a design though, it might be that some LEDs are blinking.

5. In case the QSPI Flash is loaded with the reference design, you can connect to the board with a program like PuTTY. Just open up a serial session with baud-rate of 9600 and the right COM-port(visible in Device Manager).
   You may need to press the RESET-button.
   
   
   Figure 4: Terminal(MicroBlaze output)

2.2 Reference Design Description

We provide a reference design that interacts with most of the peripheral on the module. This example design shows how to connect the different parts of the module to simplify the development of your own application. You can use it for your own design but keep in mind the overall FPGA resources and power consumption.

The reference design we use in this guide is "TE0717 test board". The most important steps to get it up and running are explained on TE0717 Test Board. The Download is available here.

The reference design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same Project. (e.g. reference design 2021.2 with vitis installation 2021.2)

The components of the reference design are illustrated in the following figure:

The Cores are connected via the AXI Interface with the MicroBlaze Processor. How they are mapped into the address space can be seen in the address editor:

Figure 6: Vivado Address Editor - Address Mapping

For example the AXI GPIO IP which has a LED1 connected to it, can be controlled with writing in software to the address 0x4000 0000.

The VIO Core enables you to control connected IOs via the Vivado Hardware Manager(like LED2).

2.3 Reference Design Hands on

The following Vivado Blockdiagram illustrates the different parts of the reference design and how they what ports are connected to hardwareoutside the FPGA.

Figure 7: Blockdesign of the provided reference design

2.3.1 Add IP to the Design

In this section we are going to add a AXI GPIO IP to the Blockdesign and connect the Carrier LEDs to the IP. After generating the Bitstream we export the design to Vitis and control the LEDs with software running on the MicroBlaze.

Neccessary steps: