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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Perihery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
- add table size as macro
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Important General Note:
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----------------------------------------------------------------------- |
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0xxx-xx ... TE0817 is an industrial /extended grade ... module ... based on Xilinx/Intel...grade MPSoC SOM integrating a Xilinx Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.
Refer to http://trenz.org/tec0850te0817-info for the current online version of this manual and other available documentation.
Key Features
Excerpt |
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- SoC/FPGA
- Device: ZU4 / ZU5 / ZU7 1)
- Engine: CG / EG / EV 1)
- Speedgrade: -1 / -2 / -3 1)
- Temperature Range: Extended / Industrial 1)
- Package: FBVB900...
- RAM/Storage
- 4 GByte DDR4 SDRAM 2)
- 2 x 64 MByte Serial Flash 3)
- EEPROM with MAC address...
- On Board
- Interface
- Power
- Dimension
- Notes
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TExxxx block diagram |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
- 4 x B2B Connector (ADM6)
up to 204 PL IO up to 65 PS MIO - 4 GTR
- 16 GTH
- I2C, JTAG
- Power
- 3.3 V power supply via B2B Connector needed 4).
- Dimension
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. 2) Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s. 3) Please, take care of the possible assembly options. 4) Dependant on the assembly option a higher input voltage may be possible.
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Block Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TE0813 block diagram |
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draw.io Diagram |
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border | true |
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diagramName | TE0817_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 641 |
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revision | 3 |
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Main Components
Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title-alignment | center |
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title | TExxxx TE0813 main components |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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- ...
- ...
- ...
Initial Delivery State
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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diagramName | Figure_OV_MC |
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simpleViewer | false |
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tbstyle | top |
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lbox | true |
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diagramWidth | 1342 |
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revision | 1 |
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- SoC, U1
- DDR4, U2, U3, U9, U12
- Quad SPI Flash, U7, U17
- Connector, JM1, JM2, JM3, JM4
- EEPROM, U28
- Clock Generator, U5
- Oscillator, U6, U32
- Power Supply, U4, U8, U10, U11, U13 ... U16, U18 ... U24, U26, U27, U29 ...U31, U33, U34, U41
Initial Delivery State
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Note |
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | EEPROM | System Controller CPLD | DDR4 SDRAM | eMMC | Programmable Clock Generator | Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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DDR4 SDRAM | not programmed |
| Quad SPI Flash | not programmed |
| EEPROM | not programmed besides factory programmed MAC address |
| Programmable Clock Generator | not programmed |
Name | B2B/Connector | Direction | Description |
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Boot Mode | Enable | Reset | JTAGSEL | PGOOD | ...
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Signals, Interfaces and Pins
B2B SoC/FPGA IOs
B2B JTAG Interface
B2B ETH Interface
B2B USB Interface
SD Card Connector
SMA Connector
MIO
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Note |
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MIO section only for SoC devices with dedicated MIO, otherwhise remove this section |
MIO Pins
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Only for SoC Modules(Xilinx MIO, for Intel and MicroChip SoC please change MIO to syntax of the manufacturer). you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.
MIO Pins are only for SoC like Zynq, U+Zynq and Versal, for other FPGA modules remove this chapter
Example:
- Table with all connectors and Designator
- List of different interfaces per connector
- IO CNT (for FPGA IOs where functionality can be changed by customer)
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Connectors
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anchor | Table_SIP_C |
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title-alignment | center |
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title | Board Connectors |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Type | Designator | Interface | IO CNT 1) | Notes |
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B2B | JM1 | MGT PL | 4 x MGT (RX/TX) |
| B2B | JM1 | HP | 52 SE / 24 DIFF |
| B2B | JM2 | MGT PS | 2 x MGT CLK |
| B2B | JM2 | MGT PS | 4 x MGT (RX/TX) |
| B2B | JM2 | CFG | JTAG |
| B2B | JM2 | CFG | MODE |
| B2B | JM3 | HD | 48 SE / 24 DIFF |
| B2B | JM3 | MGT PL | MGT CLK |
| B2B | JM3 | MIO | 65 GPIO |
| B2B | JM4 | HP | 104 SE / 48 DIFF |
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1) IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs |
Test Points
MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes1) |
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10TP1 | PWR_PL_OKJ2-120 |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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anchor | Table_SIP_TPs |
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title-alignment | center |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortEnabled | false |
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cellHighlighting | true |
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Test Point | Signal | Connected to | Notes1) |
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TP1 | PLL_SCL | pulled-up to PS_1V8 | TP2 | TP3 | PLL_SDA | pulled-up to PS_1V8TP4 | TP5 | GND |
| TP6 | PL_1V8 |
| TP7 | GND |
| TP8 | GND |
| TP9 | PL_VCCINT_IO |
| TP10 |
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: #ClockSources, #CPLD, #QuadSPIFlash |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
Power and Power-On SequenceGND |
| TP11 | PL_VCCINT |
| TP12 | PL_VCU_0V9 |
| TP13 | FP_0V85 |
| TP14 | PS_1V8 |
| TP15 | GND |
| TP16 | DDR_2V5 |
| TP17 | DDR_PLL |
| TP18 | DDR_1V2 |
| TP20 | MGTAVTT |
| TP21 | VTT |
| TP22 | PL_GT_1V05 |
| TP23 | VREFA |
| TP24 | MGTVCCAUX |
| TP25 | MGTAVCC |
| TP27 | PS_PLL |
| TP28 | PS_AVTT |
| TP29 | LP_0V85 |
| TP30 | PS_AUX |
| TP31 | PS_AVCC |
| TP34 | POR_B | pulled-up to PS_1V8 |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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On-board Peripherals
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| In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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anchor | Table_PWR_PCOBP |
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title-alignment | center |
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title | Power ConsumptionOn board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title-alignment | center |
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title | Power Distribution |
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Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Chip/Interface | Designator | Connected To | Notes |
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DDR4 SDRAM | U2, U3, U9, U12 | SoC - PS |
| Quad SPI Flash | U7, U17 | SoC - PS | Booting. | EEPROM | U28 | B2B - J2 |
| Clock Generator | U5 | SoC, B2B |
| Oscillator | U6 | Clock Generator | 25 MHz | Oscillator | U32 | SoC | 33.333333 MHz |
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Configuration and System Control Signals
Anchor |
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| Configuration and System Control Signals |
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| Configuration and System Control Signals |
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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Power-On Sequence
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anchor | Figure_PWR_PS |
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title-alignment | center |
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title | Power Sequency |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Voltage Monitor Circuit
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anchor | Figure_PWR_VMC |
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title-alignment | center |
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title | Voltage Monitor Circuit |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Power Rails
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anchor | Table_PWROV_PRCNTRL |
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title-alignment | center |
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title | Module power railsController signal. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes | |
Bank Voltages
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anchor | Table_PWR_BV |
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title-alignment | center |
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title | Zynq SoC bank voltages. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
Board to Board Connectors Page properties |
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This section is optional and only for modules.Signal Name | Direction1) | Description |
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JM1.A45 | POR_OVERRIDE | IN | Override power-on reset delay 2). | JM2.A31 | ERR_OUT | OUT | PS error indication 2). | JM2.A34 | ERR_STATUS | OUT | PS error status 2). | JM2.A35 | LP_GOOD | OUT | Low-power domain powered-up. Pulled up to 3.3VIN | JM2.A36 | PLL_SCL | IN | I2C clock | JM2.A37 | PLL_SDA | IN/OUT | I2C data | JM2.A40 | PG_VCU | OUT | Programmable logic powered-up. | JM2.A41 | EN_PSGT | IN | Enable GTR transceiver power-up. | JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47 | TCK / TDI / TDO / TMS | Signal-dependent | JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8 | JM2.B29 | PG_PSGT | OUT | GTR transceivers powered-up. | JM2.B30 | PROG_B | IN/OUT | Power-on reset 2). Pulled-up to PS_1V8. | JM2.B33 | SRST_B | IN | System reset 2). Pulled-up to PS_1V8. | JM2.B34 | INIT_B | IN/OUT | Initialization completion indicator after POR 2). Pulled-up to PS_1V8. | JM2.B37 | PG_PL | OUT | VCU powered-up. | JM2.B38 | EN_FPD | IN | Enable full-power domain power-up. | JM2.B41 | PG_FPD | OUT | Full-power domain powered-up. | JM2.B45 | PG_DDR | OUT | DDR power supply powered-up. | JM2.B46 | DONE | OUT | PS done signal 2). Pulled-up to PS_1V8. | JM2.B47 | EN_DDR | IN | Enable DDR power-up. | JM2.C31 | MR | IN | Manual reset. | JM2.C35 | EN_PL | IN | Enable programable logic power-up. | JM2.C36 | EN_GT_R | IN | Enable GTH/GTY transceiver power-up. | JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47 | MODE3..0 | IN | Boot mode selection 2):
- JTAG
- QUAD-SPI (32 Bit)
- SD1 (2.0)
- eMMC (1.8 V)
- SD1 LS (3.0)
Supported Modes depends also on used Carrier. | JM2.D33 | PG_GT_R | OUT | GTH/GTY Transceivers powered-up. | JM2.D37 | PSBATT | IN | PS RTC Battery supply voltage 2) 3). | JM2.D45 / JM2.D46 | DX_P / DX_N | - | SoC temperatur sensing diode pins 2). |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
2) See UG1085 for additional information. 3) See Recommended Operating Conditions. |
Power and Power-On Sequence
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Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power
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Scroll Title |
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
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VCCO_66 | JM1.A32 / JM1.A33 | IN |
| VREF_66 | JM1.A41 | IN |
| 3.3VIN | JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56 | IN |
| PL_1V8 | JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34 | OUT |
| PL_DCIN | JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60 / | IN |
| LP_DCDC | JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52 | IN |
| DCDCIN | JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 / | IN |
| PS_BATT | JM2.D37 | IN |
| DDR_1V2 | JM2.D47 | OUT |
| PS_1V8 | JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56 | OUT |
| GT_DCDC | JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 / | IN |
| VCCO_25 | JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9 | IN |
| VCCO_26 | JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21 | IN |
| VCCO_64 | JM4.B21 / JM4.B39 | IN |
| VREF_64 | JM4.B30 | IN |
| VCCO_65 | JM4.C21 / JM4.C39 | IN |
| VREF_65 | JM4.C30 | IN |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH/GTY for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.
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anchor | Table_BB_DH |
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title-alignment | center |
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title | Baseboard Design Hints |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. | 1 1) | PSBATT | 1.2 V ... 1.5 V | - | Battery connection. | Battery Power Domain usage. When not used, tie to GND. | 1 2) | 3.3VIN | 3.3 V (± 5 %) | - | Management power supply. | Management module power supply. 0.5 A recommended. Consider note 2) for modules with VCU and/or low-power SoC. | 2 | Processing System (PS): | Procedure for PS starting. |
| 2.1 | Low-power domain: | Bring-up for low-power domain PS. |
| 2.1.1 | LP_DCDC | 3.3 V (± 5 %) 3) | - | Low-power domain power supply. | Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution. | 2.1.2 | EN_LPD | - | PU 4), 3.3 V | Low-power domain power enable. |
| 2.1.3 | LP_GOOD | - | PU 4), 3.3 V | Low-power domain power good status. | Module power-on sequencing for low-power domain finished. | 2.2 | Full-power domain: | Bring-up for full-power domain PS. | Full-power PS domain needs powered low-power PS domain. | 2.2.1 | DCDCIN | 3.3 V (± 5 %) 3) |
| Full-power domainand GTR transceiver power supply. | Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution. | 2.2.2 | EN_FPD | 3.3 V | - | Full-power domain power enable. |
| 2.2.3 | PG_FPD | - | PU 4), 3.3 V | Full-power domain power good status. | Module power-on sequencing for full-power domain finished. | 2.2.4 | EN_DDR | 3.3 V | - | DDR memory power enable. |
| 2.2.5 | PG_DDR |
| PU 4), 3.3 V | DDR memory power good status. | Module power-on sequencing for DDR memory finished. | 2.3 | GTR Transceiver | Procedure for GTR transceiver starting. | PS transceiver usage needs powered PS (low- and full-power domain). | 2.3.1 | EN_PSGT | 3.3 V | - | GTR transceiver power enable. |
| 2.3.2 | PG_PSGT | - | PU 4), 3.3 V | GTR transceiver power good status. | Module power-on sequencing for GTR transceiver finished. | 2 | Programmable Logic (PL) | Procedure for PL starting. | PS and PL can be started independently. | 2.1 | PL_DCIN | 3.3 V (± 5 %) 3) 5) | - | Programmable logic power supply. | Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution. | 2.2 | EN_PL | - | PU 4), 3.3 V | Programmable logic power enable. |
| 2.3 | PG_PL | - | PU 4), 3.3 V | Programmable logic power good status. | Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier. | 2.4 | VCCO_25 / VCCO_26 / VCCO_64 / VCCO_65 / VCCO_66 | 6) | - | Module bank voltages. | Enable bank voltages after PG_PL deassertion. | 2.5 | PG_VCU | - | PU 4), 3.3 V | VCU power good status. |
| 3 | GTH / GTY Transceiver | Procedure for GTH / GTY transceiver starting. | PL transceiver usage needs powered PL and low-power PS domain. | 3.1 | GT_DCDC | 3.3 V (± 5 %) 3) | - | GTH / GTY transceiver power supply. | Main module power supply for GTH / GTY transceiver. 3 A recommended. Power consumption depends mainly on design and cooling solution. | 3.2 | EN_GT_R | 3.3 V | - | GTH / GTY transceiver power enable. |
| 3.3 | PG_GT_R | - | PU 4), 3.3 V | GTH / GTY transceiver power good status. |
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1) (optional) 2) On TE0813 REV01 boards it is necessary for modules with VCU and/or low-power speedgrade to either connect signal EN_PL to voltage 3.3VIN or to enable EN_PL together with 3.3VIN. This should be changed in a newer revision. 3) Dependent on the assembly option a higher input voltage may be possible. 4) (on module) 5) This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets. 6) See DS925 for additional information. |
Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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| PD:6 x 6 SoM LSHM B2B Connectors |
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Include Page |
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| PD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors |
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| PD:5.2 x 7.6 UltraSoM+ ADF6 and ADM6 B2B Connectors |
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Technical Specifications
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List of all Powerrails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
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Absolute Maximum Ratings *)
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title | PS absolute maximum ratings |
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Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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LP_DCDC | Micromodule Power | -0.300 | 6.0 | V | DCDCIN | Micromodule Power | -0.300 | 7.0 | V | GT_DCDC | Micromodule Power | -0.300 | 6.0 | V | PL_DCIN 1) | Micromodule Power | -0.300 | 4.0 | V | 3.3VIN | Micromodule Power | -0.300 | 3.600 | V | PS_BATT | RTC / BBRAM | -0.500 | 2.000 | V | VCCO_25 | HD IO Bank power supply | -0.500 | 2.000 | V | VCCO_26 | HD IO Bank power supply | -0.500 | 2.000 | V | VCCO_64 | HP IO Bank power supply | -0.500 | 3.400 | V | VCCO_65 | HP IO Bank power supply | -0.500 | 3.400 | V | VCCO_66 | HP IO Bank power supply | -0.500 | 3.400 | V | VREF_64 | Bank input reference voltage | -0.500 | 2.000 | V | VREF_65 | Bank input reference voltage | -0.500 | 2.000 | V | VREF_66 | Bank input reference voltage | -0.500 | 2.000 | V |
1) This value depends highly on DCDC U4. Higher values are possible with different DCDCs. For more information consult schematic and according datasheets. |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be different depending on assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors Include Page |
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PD:6 x 6 SoM LSHM B2B Connectors | PD:6 x 6 SoM LSHM B2B Connectors | Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMRROC |
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title-alignment | center |
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title | PS absolute maximum ratingsRecommended operating conditions. |
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orientation | portrait |
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SymbolsDescription | UnitV | Reference Document |
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LP_DCDC 1) | 3.135 | 3.465 |
V | V | VV | V | V | °C | |
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
- The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.
| DCDCIN 1) | 3.135 | 3.465 | V |
| GT_DCDC 1) | 3.135 | 3.465 | V |
| PL_DCIN 1) 2) | 3.135 | 3.465 | V |
| 3.3VIN | 3.135 | 3.465 | V |
| PS_BATT | 1.2 | 1.5 | V | See FPGA datasheet. | VCCO_25 | 1.164 | 3.399 | V | See FPGA datasheet. | VCCO_26 | 1.164 | 3.399 | V | See FPGA datasheet. | VCCO_64 | 0.97 | 1.854 | V | See FPGA datasheet. | VCCO_65 | 0.97 | 1.854 | V | See FPGA datasheet. | VCCO_66 | 0.97 | 1.854 | V | See FPGA datasheet. | VREF_64 | 0.6 | 1.2 | V | See FPGA datasheet. | VREF_65 | 0.6 | 1.2 | V | See FPGA datasheet. | VREF_66 | 0.6 | 1.2 | V | See FPGA datasheet. |
1) Dependent on the assembly option a higher input voltage may be possible. 2) This value depends highly on DCDC U4. Higher values may possible with different DCDCs. For more information consult schematic and according datasheets |
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title | Recommended operating conditions. |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Reference Document |
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V | See ???? datasheets. | V | See ???? datasheet. | V | See ???? datasheet. | V | See ???? datasheet. | V | See ???? datasheet. | V | See ???? datasheet. | V | See ???? datasheet. | °C | See ???? datasheet.
Physical Dimensions
PCB thickness: ?? mm1.74 mm (± 10 %).
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anchor | Figure_TS_PD |
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title-alignment | center |
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title | Physical Dimension |
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diagramName | Figure_TS_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 732 |
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revision | 2 |
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| Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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| image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixedImage Added |
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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Revision History
Hardware Revision History
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anchor | Figure_RV_HRN |
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title-alignment | center |
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title | Board hardware revision number. |
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_HRN | title-alignment | center |
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title | Board hardware revision number. |
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diagramName | Figure_RV_HRN |
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simpleViewer | false |
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tbstyle | top |
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lbox | true |
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diagramWidth | 188 |
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revision | 2 |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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Date | Revision | Changes | Documentation Link |
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- | REV01 | First Production Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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title | Document change history. |
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Date | Revision | Contributor | Description |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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showVersions | false |
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| Page info |
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infoType | Modified by |
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type | Flat |
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showVersions | false |
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| - <add TRM change list here>Initial Document
| -- | all | Page info |
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infoType | Modified users |
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type | Flat |
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showVersions | false |
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Disclaimer
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| IN:Legal Notices |
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| IN:Legal Notices |
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