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There are two 100Mbit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25MHz source is provided from MEMS Oscillator. PHY's are designed to operate in MII Mode. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.
| ETH1 | ETH2 | Pullup | Notes | |
|---|---|---|---|---|
| CTREF | J3.57 | J3.25 | Magnetics center tap voltage | |
| TD+ | J3.58 | J3.28 | on-board | |
| TD- | J3.56 | J3.26 | on-board | |
| RD+ | J3.52 | J3.22 | on-board | |
| RD- | J3.50 | J3.20 | on-board | |
| LED1 | J3.55 | J3.23 | on-board | |
| LED2 | J3.53 | J3.21 | on-board | |
| LED3 | J3.51 | J3.19 | on-board |
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