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Both Ethernet PHY IC's are connected to PL pins in Bank 34, all PHY IC pins are connected to FPGA pins, there is no sharing of signals for the two PHY's. PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric
PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.
PS and PL Banks
| Bank | VCCIO | B2B I/O Pins | Notes |
|---|---|---|---|
| 500 | 3.3V | 0 | |
| 501 | USER J2.4 B2B | 36 | MIO1 VREF is connected to resistor divider to support HSTL18 |
| 13 | USER J1.39 B2B | 48 | Differential routing |
| 33 | 3.3V | 33 | Single ended routing |
| 34 | 3.3V | 0 | Ethernet PHY's |
| 35 | 3.3V | 42 | Single ended routing |
| 0 | 3.3V | 4 | JTAG, note 3 pins can be used as input only from PL Fabric |
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There are two 100Mbit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25MHz source is provided from MEMS Oscillator. PHY's are designed to operate in MII Mode. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.
Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.
| ETH1 | ETH2 | Pullup | Notes | |
|---|---|---|---|---|
| CTREF | J3.57 | J3.25 | Magnetics center tap voltage | |
| TD+ | J3.58 | J3.28 | on-board | |
| TD- | J3.56 | J3.26 | on-board | |
| RD+ | J3.52 | J3.22 | on-board | |
| RD- | J3.50 | J3.20 | on-board | |
| LED1 | J3.55 | J3.23 | on-board | |
| LED2 | J3.53 | J3.21 | on-board | |
| LED3 | J3.51 | J3.19 | on-board |
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