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PS Peripherals
| Chip/Interface | IC | PS7 Peripheral | |
|---|---|---|---|
| SPI Flash | S25FL127SABMFV10 | QSPI0 | |
| I2C EEPROM | 24LC02BH | I2C0 | |
| RTC | RV-3029 | I2C0 | |
| RTC Interrupt | GPIO - MIO0 | ||
| SBC SPI | MC33908 | SPI1 | |
| SBC CAN | CAN1 | ||
| User LED | GPIO - MIO7 |
...
| MIO Pin | Mapped to | Pull up/down | Notes |
|---|---|---|---|
| 0 | GPIO | Up | RTC Interrupt |
| 1 | QSPI0 | ||
| 2 | QSPI0 | Down | |
| 3 | QSPI0 | Down | |
| 4 | QSPI0 | Down | Override to up on base for bootmode change |
| 5 | QSPI0 | Up | |
| 6 | QSPI0 | Down | |
| 7 | GPIO | Down | On-board LED |
| 8 | CAN1 TXD | Down | CAN transceiver in SBC |
| 9 | CAN1 RXD | CAN transceiver in SBC | |
| 10 | SPI1 MOSI | SBC SPI Bus | |
| 11 | SPI1 MISO | SBC SPI Bus | |
| 12 | SPI1 SCLK | SBC SPI Bus | |
| 13 | SPI1 SS0 | SBC SPI Bus | |
| 14 | I2C0 SCL | Up | On-board RTC, and EEPROM |
| 15 | I2C0 SDA | Up | On-board RTC, and EEPROM |
Recommended Peripheral mapping for MIO Voltage bank 0.
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
PL Peripherals
Both Ethernet PHY IC's are connected to PL pins in Bank 34, all PHY IC pins are connected to FPGA pins, there is no sharing of signals for the two PHY's.
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