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BankVCCIOB2B I/O PinsNotes
5003.3V0 
501USER J2.4 B2B36MIO1 VREF is connected to resistor divider to support HSTL18
13USER J1.39 B2B48Differential routing
333.3V33Single ended routing
343.3V0Ethernet PHY's
353.3V42Single ended routing
03.3V4JTAG, note 3 pins can be used as input only from PL Fabric

 

Clock sources

DesignatorICDescriptionFrequencyUsed as
U14MEMS Oscillator33.3333MHzPS7 PLL clock
U5MEMS Oscillator25MHzEthernet PHY Clock
U7RTC32.768KHzUsed by RTC, CLKOUT of RTC not connected

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