Page History

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template (note: inner scroll ignore/only only with drawIO object):

      Scroll Title
      anchor Figure_xyz title Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, use Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      
      

    • Table template:

      • Layout macro can be use for landscape of large tables
      • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

    • 
      

      Scroll Title
      anchor Table_xyz title Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

      
      

• ...

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/TI/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• Vitis/Vivado 2023.2.1
• PetaLinux
• SD
• eMMC
• ETH
• USB
• I2C
• MIPI-CSI2
• MAC from EEPROM
• User LEDs
• with Artix Reference Design Counterpart test_board_artix
  • to Artix: Chip2Chip connection
  • to Artix: 3-wire I2C Multiplexer

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of software which was used to generate the design

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  • 
    

    Scroll Title
    anchor Table_PF title-alignment center title Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Script-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

    
    

• Important set new Vivado version link on every Design update of new vivado version!
• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only

  SI5338_CLK0 Counter: 

  Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

# CRUVI LOW SPEED 1
set_property PACKAGE_PIN C12 [get_ports {C_LS1_tri_io[7]}]; #C_LS1_SDA
set_property PACKAGE_PIN A11 [get_ports {C_LS1_tri_io[6]}]; #C_LS1_SCL

set_property PACKAGE_PIN B11 [get_ports {C_LS1_tri_io[5]}]; #C_LS1_D3
set_property PACKAGE_PIN B10 [get_ports {C_LS1_tri_io[4]}]; #C_LS1_D2
set_property PACKAGE_PIN C10 [get_ports {C_LS1_tri_io[3]}]; #C_LS1_D1
set_property PACKAGE_PIN D10 [get_ports {C_LS1_tri_io[2]}]; #C_LS1_D0

set_property PACKAGE_PIN D11 [get_ports {C_LS1_tri_io[1]}]; #C_LS1_SCK
set_property PACKAGE_PIN A10 [get_ports {C_LS1_tri_io[0]}]; #C_LS1_SEL


set_property IOSTANDARD LVCMOS33 [get_ports {C_LS1_tri_io*}]

# CRUVI LOW SPEED 2
set_property PACKAGE_PIN E12 [get_ports {C_LS2_tri_io[7]}]; #C_LS2_SDA
set_property PACKAGE_PIN F14 [get_ports {C_LS2_tri_io[6]}]; #C_LS2_SCL

set_property PACKAGE_PIN E13 [get_ports {C_LS2_tri_io[5]}]; #C_LS2_D3
set_property PACKAGE_PIN D14 [get_ports {C_LS2_tri_io[4]}]; #C_LS2_D2
set_property PACKAGE_PIN C14 [get_ports {C_LS2_tri_io[3]}]; #C_LS2_D1
set_property PACKAGE_PIN D12 [get_ports {C_LS2_tri_io[2]}]; #C_LS2_D0

set_property PACKAGE_PIN C13 [get_ports {C_LS2_tri_io[1]}]; #C_LS2_SCK
set_property PACKAGE_PIN E14 [get_ports {C_LS2_tri_io[0]}]; #C_LS2_SEL

set_property IOSTANDARD LVCMOS33 [get_ports {C_LS2_tri_io*}]

set_property PACKAGE_PIN A13 [get_ports CSI_scl_io]; #CSI_SCL
set_property PACKAGE_PIN B13 [get_ports CSI_sda_io]; #CSI_SDA

set_property IOSTANDARD LVCMOS33 [get_ports CSI_*]

#B302 HD
set_property PACKAGE_PIN F11 [get_ports {CSI_GPIO_tri_io[0]}]; #CSI_GPIO0
set_property PACKAGE_PIN E11 [get_ports {CSI_GPIO_tri_io[1]}]; #CSI_GPIO1

set_property IOSTANDARD LVCMOS33 [get_ports {CSI_GPIO_tri_io*}]


set_property PACKAGE_PIN B12 [get_ports {USR_tri_io[1]}]; #V_USR_LED1
set_property PACKAGE_PIN A14 [get_ports {USR_tri_io[0]}]; #V_PL_USR_SW
set_property IOSTANDARD LVCMOS33 [get_ports {USR_tri_io*}]


### CRUVI HS1 ######
set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports {C_HS1_P[*]}]
set_property PACKAGE_PIN D27 [get_ports {C_HS1_P[11]}]; #HS1_B5
set_property PACKAGE_PIN G27 [get_ports {C_HS1_P[10]}]; #HS1_B4
set_property PACKAGE_PIN H27 [get_ports {C_HS1_P[9]}];  #HS1_B3
set_property PACKAGE_PIN J27 [get_ports {C_HS1_P[8]}];  #HS1_B2
set_property PACKAGE_PIN C25 [get_ports {C_HS1_P[7]}];  #HS1_B1
set_property PACKAGE_PIN F23 [get_ports {C_HS1_P[6]}];  #HS1_B0
set_property PACKAGE_PIN A20 [get_ports {C_HS1_P[5]}];  #HS1_A5
set_property PACKAGE_PIN E27 [get_ports {C_HS1_P[4]}];  #HS1_A4
set_property PACKAGE_PIN C22 [get_ports {C_HS1_P[3]}];  #HS1_A3
set_property PACKAGE_PIN A23 [get_ports {C_HS1_P[2]}];  #HS1_A2
set_property PACKAGE_PIN A25 [get_ports {C_HS1_P[1]}];  #HS1_A1
set_property PACKAGE_PIN B26 [get_ports {C_HS1_P[0]}];  #HS1_A0
#C27 HS1_HSO
#B28 HS1_HSI
#D24 HS1_HSRST
#D26 HS1_HSMIO

### CRUVI HS2 ######
set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports {C_HS2_P[*]}]
set_property PACKAGE_PIN C23 [get_ports {C_HS2_P[7]}]; #HS2_B5
set_property PACKAGE_PIN E22 [get_ports {C_HS2_P[6]}]; #HS2_B4
set_property PACKAGE_PIN F22 [get_ports {C_HS2_P[5]}]; #HS2_B3
# set_property PACKAGE_PIN H23 [get_ports {C_HS2_P[8]}]; #HS2_B2 not used for loopback test
set_property PACKAGE_PIN B20 [get_ports {C_HS2_P[4]}]; #HS2_B1
set_property PACKAGE_PIN D20 [get_ports {C_HS2_P[3]}]; #HS2_A5
set_property PACKAGE_PIN D24 [get_ports {C_HS2_P[2]}]; #HS2_A4
set_property PACKAGE_PIN G21 [get_ports {C_HS2_P[1]}]; #HS2_A3
set_property PACKAGE_PIN E20 [get_ports {C_HS2_P[0]}]; #HS2_A1
#E24 HS2_HSMIO
#F25 HS2_HSO


set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports {C_HS2_P[*]}]

#### ARTIX ################
set_property PACKAGE_PIN U23 [get_ports {C2C_RX_CLK}]; #U23 V_L12_P
#T24 V_L12_N
set_property PACKAGE_PIN T23 [get_ports {A_IIC_SCL_O}]; # T23 V_L13_P
set_property PACKAGE_PIN R24 [get_ports {A_IIC_SDA_I}]; # R24 V_L13_N
set_property PACKAGE_PIN R23 [get_ports {A_IIC_SDA_O}]; # R23 V_L14_P
set_property PACKAGE_PIN P24 [get_ports {C2C_TX[0]}]; #P24 V_L14_N
set_property PACKAGE_PIN M22 [get_ports {C2C_TX[1]}]; #M22 V_L15_P
set_property PACKAGE_PIN M23 [get_ports {C2C_TX[2]}]; #M23 V_L15_N
set_property PACKAGE_PIN L23 [get_ports {C2C_TX[3]}]; #L23 V_L16_P
set_property PACKAGE_PIN K24 [get_ports {C2C_TX[4]}]; #K24 V_L16_N
set_property PACKAGE_PIN K23 [get_ports {C2C_TX[5]}]; #K23 V_L17_P
set_property PACKAGE_PIN J24 [get_ports {C2C_TX[6]}]; #J24 V_L17_N
set_property PACKAGE_PIN V21 [get_ports {C2C_TX[7]}]; #V21 V_L18_P
set_property PACKAGE_PIN U22 [get_ports {C2C_TX[8]}]; #U22 V_L18_N
set_property PACKAGE_PIN T21 [get_ports {C2C_RX[0]}]; #T21 V_L19_P
set_property PACKAGE_PIN R22 [get_ports {C2C_RX[1]}]; #R22 V_L19_N
set_property PACKAGE_PIN R21 [get_ports {C2C_RX[2]}]; #R21 V_L20_P
set_property PACKAGE_PIN P22 [get_ports {C2C_RX[3]}]; #P22 V_L20_N
set_property PACKAGE_PIN N21 [get_ports {C2C_RX[4]}]; #N21 V_L21_P
set_property PACKAGE_PIN M21 [get_ports {C2C_RX[5]}]; #M21 V_L21_N
set_property PACKAGE_PIN K21 [get_ports {C2C_TX_CLK}];#K21 V_L22_P
#L22 V_L22_N
set_property PACKAGE_PIN J21 [get_ports {C2C_RX[8]}]; #J21 V_L23_P
set_property PACKAGE_PIN J22 [get_ports {C2C_RST}];   #J22 V_L23_N
set_property PACKAGE_PIN L24 [get_ports {C2C_RX[6]}]; #L24 V_L25_P
set_property PACKAGE_PIN L25 [get_ports {C2C_RX[7]}]; #L25 V_L25_N

set_property IOSTANDARD LVCMOS12 [get_ports {C2C_*}]

#N23 CLK_B702_P
#N24 CLK_B702_N

set_property IOSTANDARD LVCMOS12 [get_ports {A_IIC_*}]

• optional chapter separate

• sections for different apps

----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2022.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2022.2 xilisf_v5_11

• Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2022.2 FSBL

General:

• Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c (for hooks and board)

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0950

Hello TE0950 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate BOOT.bin.

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

ATF_CONSOLE = "pl011_1"

/include/ "system-conf.dtsi"

#include <dt-bindings/gpio/gpio.h>

/*------------------ SD --------------------*/
&sdhci1 {
	no-1-8-v;
};

/*------------------ QSPI --------------------*/
&qspi {
	num-cs = <2>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>, <1>;
		parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		spi-max-frequency = <40000000>; //40MHz no feedback pin

		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/*------------------ ETH PHY --------------------*/
&gem0 {
	phy-handle = <&phy0>;

	nvmem-cells = <&eth0_addr>;
	nvmem-cell-names = "mac-address";

	//required otherwise petalinux gives a static address here
	/delete-property/ local-mac-address;

	mdio {
		phy0: phy0@1 {
			device_type = "ethernet-phy";
			reg = <1>;

			//only needed because of reset-gpios present
			compatible = "ethernet-phy-id0141.0DD1"; //uboot: [mii read 1 2].[mii read 1 3]

			reset-names = "ETH_RESET";
			reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
			reset-assert-us = <10000>; //minimum duration according to datasheet 10ms
			reset-deassert-us = <2000>;
		};
	};
};


/*------------------ GPIO MISC --------------------*/
&gpio0 {
	gpio-line-names = 
		"", "", "", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "", "", "",
		"", "", "LPD_MIO22", "";
};
&gpio1 {
	gpio-line-names = 
		"", "", "", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "", "", "",
		"", "", "", "", "", "", "", "PMC_MIO27", "", "",
		"", "", "", "", "", "", "", "USB_OC", "", "",
		"", "", "", "", "", "", "", "", "", "",
		"", "LED0", "", "", "", "", "", "", "", "";
};

/*------------------ MIPI CSI2 --------------------*/
&mipi_csi2_axi_gpio_2 {
	gpio-line-names = "CSI_GPIO0", "CSI_GPIO1";
};

&axi_gpio_2 {
	gpio-line-names = "V_PL_USR_SW", "V_USR_LED1";
};



&mipi_csi2_mipi_csi2_rx_subsystem_0 {
	status = "disabled";
	compatible = "xlnx,mipi-csi2-rx-subsystem-5.0";
};

&mipi_csi2_v_frmbuf_wr_0 {
	status = "disabled";
};

&mipi_csi2_v_proc_ss_csc {
	status = "disabled";
	compatible = "xlnx,v-vpss-csc";
};

&mipi_csi2_v_proc_ss_scaler {
	status = "disabled";
	compatible = "xlnx,v-vpss-scaler-2.2";
};

&mipi_csi_inmipi_csi2_mipi_csi2_rx_subsystem_0 {
	clock-lanes = <0>;
	data-lanes = <1 2>;
};

&mipi_csi2_v_demosaic_0 {
	status = "disabled";
	reset-gpios = <&mipi_csi2_axi_gpio_3 3 GPIO_ACTIVE_LOW>;
};


/*------------------ USB --------------------*/
&dwc3_0 {
	dr_mode = "host";
};

/*------------------ I2C --------------------*/
&i2c0 {
	i2cswitch@70 { // Artix I2C MUX Emulations
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;
		i2c-mux-idle-disconnect;
 
		i2c_cruvi_hs1: i2c@0 { // CRUVI HS1 IIC
			reg = <0>;
		};
		i2c_cruvi_hs2: i2c@1 { // CRUVI HS2IIC
			reg = <1>;
		};
		i2c_qsfp: i2c@2 { // QSFP IIC
			reg = <2>;
		};
		i2c_fmc: i2c@3 { // FMC IIC
			reg = <3>;
		};
	};
};

&i2c2 {
	status = "okay";
  
	eeprom: eeprom@50 {
		compatible = "microchip,24aa025", "atmel,24c02";
		reg = <0x50>;
		
		#address-cells = <1>;
		#size-cells = <1>;
		eth0_addr: eth-mac-addr@FA {
			reg = <0xFA 0x06>;
		};
	};
};

  

• Note this list must be only updated, if the document is online on public doc!
• It's semi automatically, so do following
  

  • Add new row below first

  • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports