Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Versal PS Design with Linux Example. HW-Manager.
Wiki Resources page: http://trenz.org/te0950-info
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for Microblaze
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TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Select create and open delivery binary folder
Note: Folder "<project folder>/_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for BOOT.bin on QSPI Flash and image.ub, dtbos (folder) and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Not used on this example.
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. Versal Boot ROM loads PLM from SD/QSPI into OCM, 2. PLM init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze with Linux 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ... |
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) |
Option Features
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Note:
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Activated interfaces:
Type | Note |
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DDR | |
QSPI | MIO |
SD0/eMMC | MIO |
SD1/SD2.0 | MIO |
PMC_I2C | MIO |
UART1 | MIO |
LPD_IC20 | EMIO |
LPD_IC21 | MIO |
TTC0..3 | |
GEM0 | MIO |
USB0 | MIO, USB2.0 |
# CRUVI LOW SPEED 1 set_property PACKAGE_PIN C12 [get_ports {C_LS1_tri_io[7]}]; #C_LS1_SDA set_property PACKAGE_PIN A11 [get_ports {C_LS1_tri_io[6]}]; #C_LS1_SCL set_property PACKAGE_PIN B11 [get_ports {C_LS1_tri_io[5]}]; #C_LS1_D3 set_property PACKAGE_PIN B10 [get_ports {C_LS1_tri_io[4]}]; #C_LS1_D2 set_property PACKAGE_PIN C10 [get_ports {C_LS1_tri_io[3]}]; #C_LS1_D1 set_property PACKAGE_PIN D10 [get_ports {C_LS1_tri_io[2]}]; #C_LS1_D0 set_property PACKAGE_PIN D11 [get_ports {C_LS1_tri_io[1]}]; #C_LS1_SCK set_property PACKAGE_PIN A10 [get_ports {C_LS1_tri_io[0]}]; #C_LS1_SEL set_property IOSTANDARD LVCMOS33 [get_ports {C_LS1_tri_io*}] # CRUVI LOW SPEED 2 set_property PACKAGE_PIN E12 [get_ports {C_LS2_tri_io[7]}]; #C_LS2_SDA set_property PACKAGE_PIN F14 [get_ports {C_LS2_tri_io[6]}]; #C_LS2_SCL set_property PACKAGE_PIN E13 [get_ports {C_LS2_tri_io[5]}]; #C_LS2_D3 set_property PACKAGE_PIN D14 [get_ports {C_LS2_tri_io[4]}]; #C_LS2_D2 set_property PACKAGE_PIN C14 [get_ports {C_LS2_tri_io[3]}]; #C_LS2_D1 set_property PACKAGE_PIN D12 [get_ports {C_LS2_tri_io[2]}]; #C_LS2_D0 set_property PACKAGE_PIN C13 [get_ports {C_LS2_tri_io[1]}]; #C_LS2_SCK set_property PACKAGE_PIN E14 [get_ports {C_LS2_tri_io[0]}]; #C_LS2_SEL set_property IOSTANDARD LVCMOS33 [get_ports {C_LS2_tri_io*}] set_property PACKAGE_PIN A13 [get_ports CSI_scl_io]; #CSI_SCL set_property PACKAGE_PIN B13 [get_ports CSI_sda_io]; #CSI_SDA set_property IOSTANDARD LVCMOS33 [get_ports CSI_*] #B302 HD set_property PACKAGE_PIN F11 [get_ports {CSI_GPIO_tri_io[0]}]; #CSI_GPIO0 set_property PACKAGE_PIN E11 [get_ports {CSI_GPIO_tri_io[1]}]; #CSI_GPIO1 set_property IOSTANDARD LVCMOS33 [get_ports {CSI_GPIO_tri_io*}] set_property PACKAGE_PIN B12 [get_ports {USR_tri_io[1]}]; #V_USR_LED1 set_property PACKAGE_PIN A14 [get_ports {USR_tri_io[0]}]; #V_PL_USR_SW set_property IOSTANDARD LVCMOS33 [get_ports {USR_tri_io*}] ### CRUVI HS1 ###### set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports {C_HS1_P[*]}] set_property PACKAGE_PIN D27 [get_ports {C_HS1_P[11]}]; #HS1_B5 set_property PACKAGE_PIN G27 [get_ports {C_HS1_P[10]}]; #HS1_B4 set_property PACKAGE_PIN H27 [get_ports {C_HS1_P[9]}]; #HS1_B3 set_property PACKAGE_PIN J27 [get_ports {C_HS1_P[8]}]; #HS1_B2 set_property PACKAGE_PIN C25 [get_ports {C_HS1_P[7]}]; #HS1_B1 set_property PACKAGE_PIN F23 [get_ports {C_HS1_P[6]}]; #HS1_B0 set_property PACKAGE_PIN A20 [get_ports {C_HS1_P[5]}]; #HS1_A5 set_property PACKAGE_PIN E27 [get_ports {C_HS1_P[4]}]; #HS1_A4 set_property PACKAGE_PIN C22 [get_ports {C_HS1_P[3]}]; #HS1_A3 set_property PACKAGE_PIN A23 [get_ports {C_HS1_P[2]}]; #HS1_A2 set_property PACKAGE_PIN A25 [get_ports {C_HS1_P[1]}]; #HS1_A1 set_property PACKAGE_PIN B26 [get_ports {C_HS1_P[0]}]; #HS1_A0 #C27 HS1_HSO #B28 HS1_HSI #D24 HS1_HSRST #D26 HS1_HSMIO ### CRUVI HS2 ###### set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports {C_HS2_P[*]}] set_property PACKAGE_PIN C23 [get_ports {C_HS2_P[7]}]; #HS2_B5 set_property PACKAGE_PIN E22 [get_ports {C_HS2_P[6]}]; #HS2_B4 set_property PACKAGE_PIN F22 [get_ports {C_HS2_P[5]}]; #HS2_B3 # set_property PACKAGE_PIN H23 [get_ports {C_HS2_P[8]}]; #HS2_B2 not used for loopback test set_property PACKAGE_PIN B20 [get_ports {C_HS2_P[4]}]; #HS2_B1 set_property PACKAGE_PIN D20 [get_ports {C_HS2_P[3]}]; #HS2_A5 set_property PACKAGE_PIN D24 [get_ports {C_HS2_P[2]}]; #HS2_A4 set_property PACKAGE_PIN G21 [get_ports {C_HS2_P[1]}]; #HS2_A3 set_property PACKAGE_PIN E20 [get_ports {C_HS2_P[0]}]; #HS2_A1 #E24 HS2_HSMIO #F25 HS2_HSO set_property IOSTANDARD DIFF_HSTL_I_12 [get_ports {C_HS2_P[*]}] #### ARTIX ################ set_property PACKAGE_PIN U23 [get_ports {C2C_RX_CLK}]; #U23 V_L12_P #T24 V_L12_N set_property PACKAGE_PIN T23 [get_ports {A_IIC_SCL_O}]; # T23 V_L13_P set_property PACKAGE_PIN R24 [get_ports {A_IIC_SDA_I}]; # R24 V_L13_N set_property PACKAGE_PIN R23 [get_ports {A_IIC_SDA_O}]; # R23 V_L14_P set_property PACKAGE_PIN P24 [get_ports {C2C_TX[0]}]; #P24 V_L14_N set_property PACKAGE_PIN M22 [get_ports {C2C_TX[1]}]; #M22 V_L15_P set_property PACKAGE_PIN M23 [get_ports {C2C_TX[2]}]; #M23 V_L15_N set_property PACKAGE_PIN L23 [get_ports {C2C_TX[3]}]; #L23 V_L16_P set_property PACKAGE_PIN K24 [get_ports {C2C_TX[4]}]; #K24 V_L16_N set_property PACKAGE_PIN K23 [get_ports {C2C_TX[5]}]; #K23 V_L17_P set_property PACKAGE_PIN J24 [get_ports {C2C_TX[6]}]; #J24 V_L17_N set_property PACKAGE_PIN V21 [get_ports {C2C_TX[7]}]; #V21 V_L18_P set_property PACKAGE_PIN U22 [get_ports {C2C_TX[8]}]; #U22 V_L18_N set_property PACKAGE_PIN T21 [get_ports {C2C_RX[0]}]; #T21 V_L19_P set_property PACKAGE_PIN R22 [get_ports {C2C_RX[1]}]; #R22 V_L19_N set_property PACKAGE_PIN R21 [get_ports {C2C_RX[2]}]; #R21 V_L20_P set_property PACKAGE_PIN P22 [get_ports {C2C_RX[3]}]; #P22 V_L20_N set_property PACKAGE_PIN N21 [get_ports {C2C_RX[4]}]; #N21 V_L21_P set_property PACKAGE_PIN M21 [get_ports {C2C_RX[5]}]; #M21 V_L21_N set_property PACKAGE_PIN K21 [get_ports {C2C_TX_CLK}];#K21 V_L22_P #L22 V_L22_N set_property PACKAGE_PIN J21 [get_ports {C2C_RX[8]}]; #J21 V_L23_P set_property PACKAGE_PIN J22 [get_ports {C2C_RST}]; #J22 V_L23_N set_property PACKAGE_PIN L24 [get_ports {C2C_RX[6]}]; #L24 V_L25_P set_property PACKAGE_PIN L25 [get_ports {C2C_RX[7]}]; #L25 V_L25_N set_property IOSTANDARD LVCMOS12 [get_ports {C2C_*}] #N23 CLK_B702_P #N24 CLK_B702_N set_property IOSTANDARD LVCMOS12 [get_ports {A_IIC_*}] |
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 2022.2 FSBL General:
Module Specific:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0950Hello TE0950 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate BOOT.bin. |
Xilinx default PLM firmware.
Xilinx default PSM firmware.
Hello TE0950 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate BOOT.bin.
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
CONFIG_DM_RTC=y
CONFIG_NVMEM=y
create arm-trusted-firmware_%.bbappend in meta-user/recipes-bsp/arm-trusted-firmware with content
ATF_CONSOLE = "pl011_1" |
/include/ "system-conf.dtsi" #include <dt-bindings/gpio/gpio.h> /*------------------ SD --------------------*/ &sdhci1 { no-1-8-v; }; /*------------------ QSPI --------------------*/ &qspi { num-cs = <2>; flash@0 { compatible = "jedec,spi-nor"; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x8000000 0x8000000>; /* 128MB */ spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; spi-max-frequency = <40000000>; //40MHz no feedback pin #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ ETH PHY --------------------*/ &gem0 { phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; //required otherwise petalinux gives a static address here /delete-property/ local-mac-address; mdio { phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; //only needed because of reset-gpios present compatible = "ethernet-phy-id0141.0DD1"; //uboot: [mii read 1 2].[mii read 1 3] reset-names = "ETH_RESET"; reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; //minimum duration according to datasheet 10ms reset-deassert-us = <2000>; }; }; }; /*------------------ GPIO MISC --------------------*/ &gpio0 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "LPD_MIO22", ""; }; &gpio1 { gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", "PMC_MIO27", "", "", "", "", "", "", "", "", "", "USB_OC", "", "", "", "", "", "", "", "", "", "", "", "", "", "LED0", "", "", "", "", "", "", "", ""; }; /*------------------ MIPI CSI2 --------------------*/ &mipi_csi2_axi_gpio_2 { gpio-line-names = "CSI_GPIO0", "CSI_GPIO1"; }; &axi_gpio_2 { gpio-line-names = "V_PL_USR_SW", "V_USR_LED1"; }; &mipi_csi2_mipi_csi2_rx_subsystem_0 { status = "disabled"; compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; }; &mipi_csi2_v_frmbuf_wr_0 { status = "disabled"; }; &mipi_csi2_v_proc_ss_csc { status = "disabled"; compatible = "xlnx,v-vpss-csc"; }; &mipi_csi2_v_proc_ss_scaler { status = "disabled"; compatible = "xlnx,v-vpss-scaler-2.2"; }; &mipi_csi_inmipi_csi2_mipi_csi2_rx_subsystem_0 { clock-lanes = <0>; data-lanes = <1 2>; }; &mipi_csi2_v_demosaic_0 { status = "disabled"; reset-gpios = <&mipi_csi2_axi_gpio_3 3 GPIO_ACTIVE_LOW>; }; /*------------------ USB --------------------*/ &dwc3_0 { dr_mode = "host"; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@70 { // Artix I2C MUX Emulations compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x70>; i2c-mux-idle-disconnect; i2c_cruvi_hs1: i2c@0 { // CRUVI HS1 IIC reg = <0>; }; i2c_cruvi_hs2: i2c@1 { // CRUVI HS2IIC reg = <1>; }; i2c_qsfp: i2c@2 { // QSFP IIC reg = <2>; }; i2c_fmc: i2c@3 { // FMC IIC reg = <3>; }; }; }; &i2c2 { status = "okay"; eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; |
Start with petalinux-config -c kernel
Changes:
Support for Video devices (the specific models are examplary devices that were tested)
CONFIG_VIDEO_DEV=y
CONFIG_VIDEO_OV5647=y
CONFIG_VIDEO_IMX290=y
CONFIG_VIDEO_IMX219=y
CONFIG_VIDEO_XILINX_TPG=y
Start with petalinux-config -c rootfs
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
The Versal design contains a Video Processing Pipeline for Cameras connected via the MIPI CSI-2 Interface.
cam-setup.sh is a demo application to configure the Video Pipeline it is installed into the Path, and can be called from anywhere.
The Reference Design was tested and includes drivers and devicetree overlays for the following Camera Models:
The Script can currently be used to either take a screenshot or start a MJPEG-encoded video stream via Ethernet. For all parameters call cam-setup.sh -h
The script cam-setup.sh can be modified to adjust resolution or other parameters.
Example
DTBO_PATH=[path to dtbo folder, normally /run/media/[naming]-mmcblk1p1] cam-setup.sh -m rpi21 -o video
This stream can then be viewed e.g. by opening VLC on the network stream:
tcp://[board_ip]:5001
To get content of older revision got to "Change History" of this page and select older document revision number.
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