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changes.mady.by.user John Hartfiel

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changes.mady.by.user ED

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<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) --> <style> .wrapped{ width: 100% !important; max-width: 1200px !important;  } </style>
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Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"
HTML

Template Change history:

DateVersionChangesAuthor

4.2
  • Changes Xilinx to AMD
ED

4.1
  • Minor changes
    • Notes
    • Tables
ED

4.0
  • Rework for smaller TRM which can be generated faster
    • Reduce Signal Interfaces Pin
    • Reduce On Board Periphery
    • Reduce Power
    • Move Configuration Signals from Overview to own section
JH

3.12
  • Version History
    • changed from list to table
  • all
    • changed title-alignment for tables from left to center
ma

3.11
  • update "Recommended Operating Conditions" section


3.1
  • New general notes for temperature range to "Recommended Operating Conditions"


3.02
  • add again fix table of content with workaround to use it for pdf and wiki
  • Export Link for key features examples
    • Notes for different Types (with and without Main FPGA)
  • Export Link for Signals, Interfaces and Pins examples
    • Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)


3.01
  • remove fix table of content and page layout ( split page layout make trouble with pdf export)
  • changed and add note to signal and interfaces, to on board periphery section
  • ...(not finished)


3.00
  • → separation of Carrier/Module and evaluation kit TRM


2.15
  • add excerpt macro to key features


2.14
  • add fix table of content
  • add table size as macro



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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        title-alignmentcenter
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        title-alignmentcenter
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:



Scroll Ignore

Download PDF version of this document.


Overview

Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB 2.0 PHY, one GByte LPDDR4 SDRAM, 64 MByte SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

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Notes :


Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples for different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt
  • SoC/FPGA/Module
    • ...
  • RAM/Storage
    • ...
  • On Board
    • ...
  • Interface
    • ...
  • Power
    • ...
  • Dimension
    • ...
  • Notes
    • ...
  • SoC/FPGA
    • Industrial-grade Microsemi Polarfire SoC MPFS250T-1FCVG484I
  • RAM/Storage
    • 1 GByte LPDDR4
    • 64 MByte SPI Flash Memory
  • On Board
    • System Controller CPLD
    • MAC address serial EEPROM
  • Interface
    • 10/100/1000 Mbps Gigabit Ethernet PHY
    • Highly Integrated Full-Featured Hi-Speed USB 2.0 ULPI Transceiver
    • Trenz 4 x 5 module socket connectors (3x Samtec LSHM series connectors)
  • Power
    • On-board DC-DC converter
  • Dimension
    • 40 mm x 50 mm


Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
title-alignmentcenter
titleTEM0007 block diagram


Scroll Ignore

draw.io Diagram
bordertrue
diagramNameFigure_OV_BD
simpleViewertrue
width
linksauto
tbstyletop
diagramDisplayName
lboxtrue
diagramWidth644
revision14


Scroll Only

Image Added




Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    Figure template:

    Scroll Title
    anchorFigure_anchorname
    titleText
    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, objects are only linked.

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    Table template:

    Layout macro can be use for landscape of large tables


    Table_tablenameText

  • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

    • <type>_<main section>_<name>

      • type: Figure, Table
      • main section:
        • "OV" for Overview
        • "SIP" for Signal Interfaces and Pins,
        • "OBP" for On board Peripherals,
        • "PWR" for Power and Power-On Sequence,
        • "B2B" for Board to Board Connector,
        • "TS" for Technical Specification
        • "VCP" for Variants Currently in Production
        •  "RH" for Revision History
      • name: custom, some fix names, see below
    • Fix names:

      • "Figure_OV_BD" for Block Diagram

      • "Figure_OV_MC" for Main Components

      • "Table_OV_IDS" for Initial Delivery State

      • "Table_PWR_PC" for Power Consumption

      • "Figure_PWR_PD" for Power Distribution
      • "Figure_PWR_PS" for Power Sequence
      • "Figure_PWR_PM" for Power Monitoring
      • "Table_PWR_PR" for Power Rails
      • "Table_PWR_BV" for Bank Voltages

      • "Table_TS_AMR" for Absolute_Maximum_Ratings

      • "Table_TS_ROC" for Recommended_Operating_Conditions

      • "Figure_TS_PD" for Physical_Dimensions
      • "Table_VCP_SO" for TE_Shop_Overview

      • "Table_RH_HRH" for Hardware_Revision_History

      • "Figure_RH_HRN" for Hardware_Revision_Number
      • "Table_RH_DCH" for Document_Change_History
  • Use Anchor in the document: add link macro and add "#<anchorname>
  • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
    • Scroll Title
    anchor
    Figure_OV_MC
    title-alignmentcenter
    title
    TEM0007 main components


    scroll-
    tablelayout
    ignore
    orientation

    draw.io Diagram

    portrait

    border

    sortDirection

    true

    		ASC
    repeatTableHeadersdefault
    stylewidths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue
    ExampleComment
    12
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    -----------------------------------------------------------------------

    Page properties
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    Note for Download Link of the Scroll ignore macro:

    Scroll Ignore

    Download PDF version of this document.

    Scroll pdf ignore

    Table of Contents

    Table of Contents

    Overview

    Trenz Electronic TEM0007 module is an industrial-grade FPGA micromodule integrating a Microsemi Polarfire SoC FPGA, Gigabit Ethernet PHY, USB 2.0 PHY, one GByte LPDDR4 SDRAM, 64 MByte SPI Flash memory for configuration and operation, and power supply. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.

    Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.

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    Notes :

    ...

    diagramNameTEM0007_OV_MC
    simpleViewerfalse
    width
    linksauto
    tbstyletop
    lboxtrue
    diagramWidth641
    revision4


    Scroll Only

    Image Added




    1. Microsemi Polarfire SoC MPFS250T, U2
    2. 1 GByte LPDDR4 SDRAM, U6
    3. Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U7
    4. Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver, U11
    5. Lattice Semiconductor MachXO2 System Controller CPLD, U1
    6. B2B Connector Samtec Razor Beam, JM1...3
    7. EEPROM, U10
    8. Serial NOR Flash, U3

    Initial Delivery State

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    Note

    Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty


    Scroll Title
    anchorTable_OV_IDS
    title-alignmentcenter
    titleInitial delivery state of programmable devices on the module

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Storage device name

    Content

    Notes

    SPI NOR Flash, U3

    		Not programmed
    EEPROM, U10Pre-programmed globally unique MAC
    System Controller CPLD, U1Standard firmware




    Signals, Interfaces and Pins

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    For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

    Note
    • Table with all connectors and Designator
    • List of different interfaces per connector
    • IO CNT (for FPGA IOs where functionality can be changed by customer)


    Connectors

    Scroll Title
    anchorTable_SIP_C
    title-alignmentcenter
    titleBoard Connectors

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Connector TypeDesignatorInterfaceIO CNTNotes


























    Test Points

    Note:
     'description: Important components and connector or other Features of the module
    → please sort and indicate assembly options

    Key Features'  must be split into 6 main groups for modues:

    • SoC/FPGA
      • Package:
      • Speed:
      • Temperature:
    • RAM/Storage
      • E.g. SDRAM, SPI
    • On Board
      • E.g. CPLD, PLL
    • Interface
      • E.g. ETH, USB, B2B, Display port
    • Power
      • E.g. Input supply voltage
    • Dimension

    Key Features'  must be split into 6 main groups for carrier:

    • Modules
      • TE0808, TE807, TE0803,...
    • RAM/Storage
      • E.g. SDRAM, SPI
    • On Board
      • E.g. CPLD, PLL
    • Interface
      • E.g. ETH, USB, B2B, Display port
    • Power
      • E.g. Input supply voltage
    • Dimension
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    • SoC/FPGA
      • Industrial-grade Microsemi Polarfire SoC MPFS250T-1FCVG484I
    • RAM/Storage
      • 1 GByte LPDDR4
      • 64 MByte SPI Flash Memory
    • On Board
      • System Controller CPLD
      • MAC address serial EEPROM
    • Interface
      • 10/100/1000 Mbps Gigabit Ethernet PHY
      • Highly Integrated Full-Featured Hi-Speed USB 2.0 ULPI Transceiver
      • Trenz 4 x 5 module socket connectors (3x Samtec LSHM series connectors)
    • Power
      • On-board DC-DC converter
    • Dimension
      • 40 mm x 50 mm

    ...

    you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

    Example:

    Test PointSignalNotes1)
    TP1PWR_PL_OK

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.
    Scroll Title
    anchorTable_SIP_TPs
    title-alignmentcenter
    titleTest Points Information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Test PointSignalNotes1)
    TP1

    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    On-board Peripherals

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .
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    Notes :

    In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

    Example:

    Chip/InterfaceDesignatorConnected ToNotes
    ETH PHYU10
    • B2B connector J1
    • SoC MIO
    		Gigabit ETH PHY

    add drawIO object here.

    Note


    Scroll Title
    anchorTable_OBP
    title-alignmentcenterFigure_OV_BD
    titleTEM0007 block diagramOn board peripherals

    scroll-

    ignore
    draw.io Diagram
    bordertrue
    diagramNameFigure_OV_BD
    simpleViewertrue
    width
    linksauto
    tbstyletop
    diagramDisplayName
    lboxtrue
    diagramWidth644
    revision14
    Scroll Only

    Image Removed

    ...

    tablelayout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Chip/InterfaceDesignatorConnected ToNotes





    Page properties
    hiddentrue
    idComments

    For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals


    Configuration and System Control Signals

    For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .
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    • Overview  all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
    • In case it's connected to CPLD always link to CPLD description and add not from the  current implementation here(in case it's available)

    Notes :

    • Picture of the PCB (top and bottom side) with labels of important components
    • Add List below
    Note
    Scroll Title
    anchorFigureTable_OV_MCCNTRL
    title-alignmentcenter
    titleTEM0007 main componentsController signal.

    scroll-

    ignore
    draw.io Diagram
    bordertrue
    diagramNameTEM0007_OV_MC
    simpleViewerfalse
    width
    linksauto
    tbstyletop
    lboxtrue
    diagramWidth641
    revision4
    Scroll Only

    Image Removed

    1. Microsemi Polarfire SoC MPFS250T, U2
    2. 1 GByte LPDDR4 SDRAM, U6
    3. Integrated 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U7
    4. Highly Integrated Full Featured Hi-Speed USB 2.0 ULPI Transceiver, U11
    5. Lattice Semiconductor MachXO2 System Controller CPLD, U1
    6. B2B Connector Samtec Razor Beam, JM1...3
    7. EEPROM, U10
    8. Serial NOR Flash, U3

    ...

    tablelayout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Connector+Pin

    Signal Name

    		Direction1)Description




    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.

    Power and Power-On Sequence

    Page properties
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    Enter the default value for power supply and startup of the module here.

    • Order of power provided Voltages and Reset/Enable signals

    Link to Schematics, for power images or more details


    Power Rails

    Page properties
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    List of all power rails which are accessible by the customer

    • Main Power Rails and Variable Bank Power

    Notes :

    Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty



    Scroll Title
    anchorTable_OV_IDSPWR_PR
    title-alignmentcenter
    titleModule power rails.titleInitial delivery state of programmable devices on the module

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Storage device name

    Content

    Notes

    SPI NOR Flash, U3

    		Not programmed

    -

    EEPROM, U10Pre-programmed globally unique MAC

    -

    System Controller CPLD, U1Standard firmware-

    Signals, Interfaces and Pins

    ...

    hiddentrue
    idComments

    Notes :

    ...

    • SD
    • USB
    • ETH
    • FMC
    • ...


    Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
















    1) Direction:

      • IN: Input from the point of view of this board.
      • OUT: Output from the point of view of this board.


    Recommended Power up Sequencing

    Page properties
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    List baseboard design hints for final baseboard development.

    Scroll Title
    anchorTable_BB_DH
    title-alignmentcenter
    titleBaseboard Design Hints

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue


    SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes



















































    ED: TODO → Following needs to be updated to new TRM style.

    ...

    Board to Board (B2B) I/Os

    ...

    Scroll Title
    anchorTable_OBP_USB
    titleGeneral Overview of the USB PHY Signals

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    PHY PinConnected toB2BNotes

    DP - 18,

    OTG-D_P

    		JM3 - 47USB data line
    DM - 19OTG-D_NJM3 - 49USB data line
    CPEN - 17VBUS_ENJM3 - 53External USB power switch
    VBUS - 22VBUSJM3 - 55
    ID - 23IDJM3 - 51


    Test Points

    Scroll Title
    anchorTable_OBP_TestPoints
    titleTest Points Information

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Test PointSignalConnected toNotes
    1+3.3VHigh-Side Switch, U14
    2+2.5VVoltage Regulator, U21
    3+2.5V_XCVRVoltage Regulator, U22
    4+1.8VVoltage Regulator, U20
    5+1.8V_VDDHigh-Side Switch, U13
    6+1.1V_LPDDR4Voltage Regulator, U18
    7+1.0VVoltage Regulator, U19
    8VDDAUX1Power Switch, U16
    9AVDD18Voltage Regulator, U7
    10AVDD33Inductor, L6
    11DVDD1V0Voltage Regulator, U7
    12F_TRSTBFPGA Bank 3



    On-board Peripherals

    Page properties
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    Notes :

    • add subsection for every component which is important for design, for example:
      • Two 100 Mbit Ethernet Transciever PHY
      • USB PHY
      • Programmable Clock Generator
      • Oscillators
      • eMMCs
      • RTC
      • FTDI
      • ...
      • DIP-Switches
      • Buttons
      • LEDs

    ...

    Scroll Title
    anchorTable_OBP
    titleOn board peripherals

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Chip/InterfaceDesignatorNotes
    94486264System Controller CPLDU194486264
    Gigabit EthernetU794486264
    USB PHYU11
    94486264LPDDR4 SDRAMU6
    94486264EEPROMU1094486264
    SPI Flash MemoryU3
    94486264OscillatorsU4...5, U12


    System Controller CPLD

    ...

    Scroll Title
    anchorTable_OBP_CLK
    titleOsillators

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    DesignatorDescriptionFrequencyNote
    U4MSS REFCLK125 MHz
    U5SERDES CLK125 MHz
    U12USB52 MHz


    Power and Power-On Sequence

    Page properties
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    In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

    • Power on-sequence
    • Power distribution
    • Voltage monitoring circuit


    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


    ...

    Scroll Title
    anchorFigure_PWR_VMC
    titleVoltage Monitor Circuit


    Scroll Ignore

    draw.io Diagram
    bordertrue
    diagramNameTEM0007_PWR_VM
    simpleViewerfalse
    width
    linksauto
    tbstyletop
    lboxtrue
    diagramWidth481
    revision2


    Scroll Only


    Power Rails

    Scroll Title
    anchorTable_PWR_PR
    titleModule power rails.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue


    Power Rail Name

    B2B Connector

    JM1 Pin

    B2B Connector

    JM2 Pin

    		DirectionNotes
    VIN1, 3, 52, 4, 6, 8InputSupply voltage from the carrier board
    3.3VIN13, 15-InputSupply voltage from the carrier board
    3.3VIN-91OutputJTAG reference voltage
    +1.8V39-OutputInternal +1.8V voltage level

    VCCIOB

    		-1, 3InputGeneral purpose I/O bank voltage
    VCCIOD-7, 9InputHigh speed I/O bank voltage (max. +1.8 V)
    +3.3V-10, 12OutputInternal +3.3 V voltage level


    ...